Presentation on theme: "It’s all about latency Henk Neefs Dept. of Electronics and Information Systems (ELIS) University of Gent."— Presentation transcript:
It’s all about latency Henk Neefs Dept. of Electronics and Information Systems (ELIS) University of Gent
Overview Introduction of processor model Show importance of latency Techniques to handle latency Quantify memory latency effect Why consider optical interconnects? Latency of an optical interconnect Conclusions
Out-of-order processor pipeline I-cache fetchdecode instruction window rename architectural register file LD ST execution units ‘future’ register file INT in-order retirement
Branch latency I-cache fetchdecode instruction window rename LD ST execution units ‘future’ register file INT BR time ADDORSTXORLD ORBRSTXORLD... BR latency
Eliminate branch latency By prediction: predict outcome of branch => eliminate dependency (with a high probability) By predication: convert control dependency to data dependency => eliminate control dependency
Increase performance by eliminating/reducing load latency: –By prefetching: predict the next miss and fetch the data to e.g. L1-cache –By address prediction: address known earlier => load executed earlier => data early in register file or reducing sensitivity to load latency: – by fine-grain multithreading
Some prefetch techniques Stride prefetching: search for pattern with constant stride e.g. walking through a matrix (row- or column-order) Markov prefetching: recurring patterns of misses 2031425364 stride: 11 miss history prediction 10 110 15 12 100 …...
Prefetching and sensitivity Factors of “performance sensitivity to latency” increase with stride-prefetching:
Latency is important: generalization to other processor architectures Consider schedule of program: time Present in every program execution: Latency of instruction execution Latency of communication => latency important whatever processor architecture
Optical interconnects (OI) Mature components: – Vertical-Cavity Surface Emitting Lasers (VCSELs) – Light Emitting Diodes (LEDs) Very high bandwidths Are replacing electronic interconnects in telecom and networks Useful for short inter-chip and even intra-chip interconnects?
OI in processor context At levels close to processor core, latency is very important => latency of OI determines how far OI penetrates in the memory hierarchy What is the latency of an optical interconnect?
An optical link Total latency = buffer latency + VCSEL/LED latency + time of flight + receiver latency LED/VCSEL buffer/modulation/bias fiber or light conductor receiver diode transimpedance amplifier
VCSEL characteristics A small semiconductor laser Carrier density should be high enough for lasing action
Total VCSEL link latency consists of Buffer latency Parasitic capacitances and series resistances of VCSEL and pads Threshold carrier density build up From low optical output to final optical output (intrinsic latency) Time of flight (TOF) Receiver latency
Total optical link latency CMOS: 0.6 m0.25 m0.6 m0.25 m @ 1 mW
Conclusions When combining performance sensitivity and optical latency we conclude: –optical interconnects are feasible to main memory and for multiprocessors –for interconnects close to processor core, optical interconnects have too high latency with present (telecom) devices, drivers and receivers => but now evolution to lower latency devices, drivers and receivers is taking place... For more information on the presented results: Henk Neefs, Latentiebeheersing in processors, PhD Universiteit Gent, January 2000 www.elis.rug.ac.be/~neefs
Your consent to our cookies if you continue to use this website.