Presentation on theme: "1 CMPT 300 Introduction to Operating Systems Virtual Memory Sample Questions."— Presentation transcript:
1 CMPT 300 Introduction to Operating Systems Virtual Memory Sample Questions
0. Page Table Q: Consider a system with 32-bit virtual address. The virtual memory is implemented by paging, and the page size is 4KB. A user process generates the virtual address 0x11123456. What is the page table index for this virtual address? A: Since the page size is 2^12, the page table size is 2^20. The virtual address in binary form is 0001 0001 0001 0010 0011 0100 0101 0110. The low-order 12 bits 0100 0101 0110 are used as the offset into the page, while the remaining 20 bits 0001 0001 0001 0010 0011 are used as the index into the page table, or 0x11123. 2
1.1 Inverted Page Table Consider a system with 32-bit virtual address space, and 4 MB of physical memory. The page size is 8KB (8192-byte). The system uses an Inverted Page Table (IPT). Q: How many bits is each VPN? How many bits is each PPN? Describe what PTE (page table entry) looks like. How many PTEs (page table entries) does the IPT contain? (Remember: PT is indexed by VPN and contains PPN; IPT is indexed by PPN and contains VPN.) A: The virtual address consists of VPN: 19 bits; Offset: 13 bits 2^13=8KB, hence offset is 13 bits; the total virtual address length is 32 bits, hence VPN is 32-3=19 bits. There are a total of 4MB/8KB=512 physical pages, hence the PPN is 9 bits (2^9=512). The IPT contains 512 PTEs. IPT maps from PPN to VPN. It contains 512 PTEs. Each PTE contains a 19-bit field for VPN, plus another field for Process ID, plus additional bits for protection etc. (Offset is not stored in page tables) 3
1.2 Page Table Consider a system with 32-bit virtual address space, and 4 MB of physical memory. The page size is 8KB (8192-byte). The system uses a regular Page Table. Q: How many bits is each VPN? How many bits is each PPN? Describe what PTE (page table entry) looks like. How many PTEs (page table entries) does the PT contain? A: Same as before, VPN: 19 bits; PPN: 9 bits. Each PTE contains a 9-bit field for PPN, plus additional protection bits for protection etc. There are a total of 2^32/2^13=2^19 virtual pages, hence the PT contains 2^19 PTEs. Q: Why is there not a field for Process ID? A: Each process has its own separate page table. 4
2. 1 Page Table Consider a system with 32-bit virtual address using two-level page tables for address translation. The format of the virtual address, physical address, and PTE (page table entry) are as shown. Assume each PTE in both 1 st and 2 nd level PTs is 2 bytes, including all permission bits. Size of physical memory is 4MB. Q: How large is each page? How many physical pages in total? How many bits in PPN? A: Page size: 2^12 bytes =4 KB; Total number of physical pages is 4MB/4KB=1K=2^10 # bits in PPN is 10. 5 4KB 1K PTEs 1K PTEs 32-bit address: P1 indexP2 indexpage offset 10 12
2. 2 Page Table Q: What is the largest possible memory needed for storing all page tables? A: There is one page table at the first level, and up to 2^10 = 1K page tables at the 2 nd level. Each PTE is 2 bytes. Size of the 1 st level page table is 2*(2^10) bytes = 2KB. Size of each 2 nd level table is also 2*(2^10) bytes = 2KB. All in all, the page tables use 2KB + 1024 * 2KB = 2050 KB of memory. 6 4KB 1K PTEs 1K PTEs 32-bit address: P1 indexP2 indexpage offset 10 12
2. 3 Page Table Q: Consider a process that is using 512KB of physical memory. What is the minimum number of page tables used by this process? What is the maximum number of page tables this process might use? A: The process uses 512KB / 4 KB = 128 physical pages. Since each 2 nd level page can hold up to 1K PTEs, in the best case scenario the process is covered by a single 2 nd level PT. we use only 2 page tables: 1st level PT + a 2nd level PT. In the worst case, the process may use a little bit of every physical page (e.g., 0.5 KB of each physical page), and all page tables will be populated. Thus, the process ends up using 1 + 1024 = 1025 page tables. 7 4KB 1K PTEs 1K PTEs 32-bit address: P1 indexP2 indexpage offset 10 12
2. 4 Page Table Q: Assume that instead of two-level PTs, we use an inverted PT for address translation. How many entries are used in the inverted table by a process using 512KB of physical memory? A: The inverted table contains one entry per physical page, hence it has 2^10=1K entries. In the worst case, the process uses all physical pages, which yields 1K entries. In the best case, the process fully uses each physical page, which yields 128 entries.
3. TLB Consider a system with the page tables stored in memory. If a memory reference takes 200 nanoseconds, how long does a paged memory reference take? If we add a TLB, and 75 percent of all page-table references are found in the TLB, what is the effective memory reference time? (Assume that finding a page-table entry in the TLB takes zero time, if TLB hit.) A: 400 ns; 200 ns to access the page table and 200 ns to access the word in memory. Effective access time = 0.75 (200 ns) + 0.25 (400 ns) = 250 ns. 9
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