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Computer Systems An Integrated Approach to Architecture and Operating Systems Chapter 2 Processor Architecture ©Copyright 2008 Umakishore Ramachandran.

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Presentation on theme: "Computer Systems An Integrated Approach to Architecture and Operating Systems Chapter 2 Processor Architecture ©Copyright 2008 Umakishore Ramachandran."— Presentation transcript:

1 Computer Systems An Integrated Approach to Architecture and Operating Systems Chapter 2 Processor Architecture ©Copyright 2008 Umakishore Ramachandran and William D. Leahy Jr.

2 Overview Architectural Issues – Instruction Set – Machine Organization Historical Perspective – Programming primarily in Assembly Language – Development of sophisticated compiler technology – Development of Operating Systems

3 Processor Design Hardware resources are like letters Instruction set is like words Instruction set is key differentiation between different processors (e.g. Intel x86 & Power PC)

4 Instruction Set Architecture CFortranAda Compiler Assembly Language Assembler etc.BasicJava Compiler Interpreter Byte Code Executable HW Implementation 1 HW Implementation N HW Implementation 2

5 Instruction Set Design Goals Easy to Build Hardware Hardware Compiler(s) Compiler(s)MaximizePerformanceMaximizePerformanceMinimizeCostMinimizeCost

6 High Level language Constructs High Level Language Constructs a = b + c; /* add b and c and place in a */ d = e – f; /* subtract f from e and place in d */ x = y & z; /* AND y and z and place in x */ Assembly Language Constructs add a, b, c; a  b + c sub d, e, f; d  e – f and x, y, z; x  y & z

7 Where to Keep the Operands Processor Memory Devices Processor Memory Devices ALU Registers

8 Memory Address Specification Need a way of specifying an address in an instruction? Problem: Addresses are as long (if not longer) than the length of the instruction One solution: Store a register number of a register containing the address Include an offset in the space left over processor Memory r2 b

9 Base + Offset ld rdest, offset(rbase) ld r2, 3(r1) Semantics – Value in rbase is added to offset forming an effective address – The contents of that effective address are fetched and placed into rdest Register transfer language r2 ← M[(r1) + 3]

10 Operand Width How many bits does a load instruction fetch from memory? How many should it fetch? High level languages typically support multiple data types and thus for efficiency most processors will have the ability to fetch different sized “chunks” of data The minimum is usually 8, the maximum has continually increased. 8? 16? 32? 64?4? 1?more?

11 Other Questions Arithmetic & logical operations can be performed on what size data? The processor can move what size data to and from memory? What is the size data the register can hold?

12 Endianess How should bytes be numbered? 100101102103 104105106107 108109110111 112113114115 100101102103 104105106107 108109110111 112113114115 Byte Word ? And why does it matter? Big Endian Little Endian

13 Endianess Different manufacturers have “standardized on different endianesses Normally on a single machine this is not an issue. – Especially if data is handled commensurate with the way it was declared – Can it be an issue In a networked environment it can could cause big problems

14 Packing Operands Word Operand Alignment Consider struct { chara; charb[3]; } 100 104 a +0 +1 +2+3 b[2]b[1]b[0] b[2]ab[0]b[1] 103 102 101 100

15 Packing Operands Word Operand Alignment Consider struct { chara; intb; } 100 104 a b lsb b msb b…b… b…b… +0 +1 +2+3 100 104 a b lsb b msb b…b… b…b… +0 +1 +2+3

16 Compiling High Level Data Abstractions Consider struct { inta; charc; intd; longe; } Given the address of the structure can we access the fields using base+offset addressing?

17 Compiling High Level Data Abstractions Now consider int a[1000]; Can individual array elements be accessed using base+offset addressing? a[6] = a[6] + 3; a[j] = a[i] + 3; Perhaps an instruction that formed an effective address by adding two registers together would be useful?

18 Compiling Conditional Statements In what order are program statements normally executed? How do we know what instruction to execute next? How can we handle this type high-level language construct: if(x==y) z = 7;

19 Compiling Conditional Statements if(x==y) z = 7; Steps to execute – Evaluate the predicate (x==y) – If false change the normal flow of control to skip the x = 7; statement and continue execution – If true execute the z = 7; and then continue execution

20 Compiling Conditional Statements Need an instruction that will evaluate a predicate and change program flow As an example beq r1, r2, offset – Semantics: if the contents of registers r1 and r2 are equal add the offset to the (already incremented) PC and store that address in the PC

21 Compiling Conditional Statements C if(a==b) c = d + e; else c = f + g; Assembly beq r1, r2, then add r3, r6, r7 beq r1, r1, skip* then add r3, r4, r5 skip … * Effectively an unconditional branch Assuming r1 = a r2 = b r3 = c r4 = d r5 = e r6 = f r7 = g

22 Compiling Loops C while(j ! = 0) { /* loop body */ t = t + a[j--]; } Assembly beq r1,r0,done ; loop body … done …

23 Compiling Switch Statements if(n==0) x=a; else if(n==1) x=b; else if(n==2) x=c; else x=d; Switch (n) { case 0: x=a; break; case 1: x=b; break; case 2: x=c; break; default: x=d; } Do these produce essentially equivalent assembly code? Do these produce essentially equivalent assembly code?

24 Compiling Procedure Calls int main() { return-value = foo(actual-parms); /* continue upon returning from * foo */ } int foo(formal-parameters) { /* code for function foo */ return( ); }

25 Issues with Compiling 1.Preserve caller state (registers) 2.Pass actual parameters 3.Save the return address 4.Transfer control to callee 5.Allocate space for callee’s local variables 6.Produce return value(s); give to caller 7.Return

26 Caller State Where should caller’s register values be saved? – Why do we even need to save them? – Dedicated registers? What limitation might arise? – Who should save what? Caller saved registers Callee saved registers

27 What’s Left? Parameter passing – Dedicated registers – Stack Return address – JAL Instruction Transfer Control – Change PC – JAL Instruction

28 What’s Left? Local variables? – Stack Return value(s) – Dedicated registers – Stack Returning to point of call – JAL back through link

29 Software Conventions Registers s0-s2 are the caller’s s registers Registers t0-t2 are the temporary registers Registers a0-a2 are the parameter passing registers Register v0 is used for return value Register ra is used for return address Register at is used for target address Register sp is used as a stack pointer

30 Activation Record Used to store – Caller saved registers – Additional parameters – Additional return values – Return address – Callee saved registers – Local variables

31 Step 1. Caller saves any of registers t0-t3 on the stack (if it needs the values in them upon return). Stack Pointer STACK From t registers Saved t Registers

32 Step 2. Caller places the parameters in a0-a2 (using the stack for additional parameters if needed). Stack Pointer Saved t Registers Additional parameters STACK From function call

33 Step 3. Caller allocates space for any additional return values on the stack Stack Pointer STACK Additional return values Saved t Registers Additional parameters

34 Step 4. Caller saves ra Stack Pointer ra STACK Additional return values From ra Saved t Registers Additional parameters

35 Step 5. Caller executes JAL at, ra (no effect on stack) Stack Pointer STACK ra Additional return values Saved t Registers Additional parameters

36 Step 6. Callee saves any of registers s0-s3 that it plans to use during its execution on the stack. Stack Pointer Saved s Registers STACK ra Additional return values From s registers Saved t Registers Additional parameters

37 Step 7. Callee allocates space for any local variables on the stack Stack Pointer Local variables STACK Saved s Registers ra Additional return values Saved t Registers Additional parameters

38 Step 8. Prior to return, Callee restores any saved s0-s3 registers from the stack Stack Pointer STACK Saved s Registers ra Additional return values To S registers Saved t Registers Additional parameters

39 Step 9. Upon return, Caller restores ra Stack Pointer STACK ra Additional return values To ra Saved t Registers Additional parameters

40 Step 10. Caller stores additional return values as desired Stack Pointer STACK Additional return values As desired Saved t Registers Additional parameters

41 Step 11. Upon return, Caller moves stack pointer to discard additiona parameters Stack Pointer STACK Saved t Registers Additional parameters

42 Step 12. Upon return, Caller restores any saved t0-t3 registers from the stack Stack Pointer STACK To t registers Saved t Registers

43 Stack Pointer Activation Stack Frame for baz Activation Stack Frame for bar Activation Stack Frame for foo Activation Stack Frame for main Local variables Saved s Registers ra Additional return values Saved t Registers Additional parameters

44 Recursion Does recursion require any additional instruction set architecture items?

45 Frame Pointer During execution of given module it is possible for the stack pointer to move. Since the location of all items in a stack frame is based on the stack pointer it useful to define a fixed point in each stack frame and maintain the address of this fixed point in a register called the frame pointer This necessitates storing the old frame pointer in eahc stack frame (i.e caller’s frame pointer)

46 New Step 6. Callee stores old frame pointer then copies contents of stack pointer into frame pointer. Frame Pointer Old Frame Pointer STACK ra Additional return values Stack Pointer* *Stack pointer can eventually be anywhere Saved t Registers Additional parameters

47 Instruction Set Architecture Choices Specific set of arithmetic and logic instructions Addressing modes Architectural style Memory layout of the instruction. Drivers – Technology trends – Implementation feasibility – Goal of elegant/efficient support for high-level language constructs.

48 Instructions MIPS – All loads and stores 32 bits – Special instructions exist for extracting bytes DEC Alpha – Instructions for loading and storing different sizes Some architectures have predefined values – e.g. 0, 1, etc. DEC Vax – Single instruction to load or store all registers

49 Addressing Modes Additional modes – Indirect addressing ld @(ra) Pseudo-direct addressing – Address is formed from first 6 bits of PC and last 26 bits of instruction

50 Architecture Styles Stack oriented – Burroughs Memory oriented – IBM s/360 et al Register oriented – MIPS, Alpha, ARM Hybrid – Intel x86, Power PC

51 Instruction Format Zero Operand Instructions – Halt, NOP – Stack machines: Add One Operand Instructions – Inc, Dec, Neg, Not – Accumulator machines: Load M, Add M Two Operand Instructions – Add r1, r2 (i.e. r1 = r1 + r2) – Mov r1, r2 Three Operand Instructions – Add r1, r2, r3 – Load rd, rb, offset

52 Instruction Format Fixed Length Instructions Pros – Simplifies implementation – Can start interpreting Cons – May waste space – May need additional logic in datapath – Limits instruction set designer Variable Length Instructions Pros – No wasted space – Less constraints on designer – More flexibility opcodes, addressing modes and operands Cons – Complicates implementation

53 LC-2200 Instruction Set 32-bit Register-oriented Little-endian Fixed length instruction format 16 general-purpose registers Program counter (PC) register. All addresses are word addresses.

54 Instruction Format R-type instructions – add and nand I-type instructions – addi, lw, sw, and beq J-type instruction – jalr O-type instruction – halt

55 Instruction Format R-type instructions (add, nand): bits 31-28: opcode bits 27-24: reg X bits 23-20: reg Y bits 19-4: unused (should be all 0s) bits 3-0: reg Z I-type instructions (addi, lw, sw, beq): bits 31-28: opcode bits 27-24: reg X bits 23-20: reg Y bits 19-0: Immediate value or address offset (a 20-bit, 2s complement number with a range of -524288 to +524287) J-type instructions (jalr): bits 31-28: opcode bits 27-24: reg X (target of the jump) bits 23-20: reg Y (link register) bits 19-0: unused (should be all 0s) O-type instructions (halt): bits 31-28: opcode bits 27-0: unused (should be all 0s)

56 LC-2200 Register Set Reg # NameUsecallee-save? 0 $zeroalways zero (by hardware)n.a. 1 $atreserved for assemblern.a. 2 $v0return valueNo 3 $a0argumentNo 4 $a1argumentNo 5 $a2argumentNo 6 $t0TemporaryNo 7 $t1TemporaryNo 8 $t2TemporaryNo 9 $s0Saved registerYES 10 $s1Saved registerYES 11 $s2Saved registerYES 12 $k0reserved for OS/trapsn.a. 13 $spStack pointerNo 14 $fpFrame pointerYES 15 $rareturn addressNo

57 Issues Influencing Processor Design Instruction Set Applications Other – Operating system – Support for modern languages – Memory system – Parallelism – Debugging – Virtualization – Fault Tolerance – Security

58 Instruction Set Over-arching concern: Compiling high level language constructs into efficient machine code But other factors are in play – Market pressure – Performance – Technology workarounds

59 Influence of Applications on Instruction Set Design Number crunching requires efficient floating point – Development of floating point hardware Media applications deal with streaming data – Intel MMX extensions Gaming requires sophisticated graphic processing – High end games now include GPU chips

60 Other Issues Driving Processor Design Operating system Modern languages: Java, C++ and C# Memory system Parallelism Debugging Virtualization Fault tolerance Security

61 Summary High-level language constructs shape ISA Support needed in the ISA for compiling basic program statements (assignment, loops, conditionals, etc.) Registers Addressing modes Software conventions Software stack/procedure calls Extensions to minimal ISA’s Other design issues


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