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Computing Machinery Chapter 7: Register Transfers.

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Presentation on theme: "Computing Machinery Chapter 7: Register Transfers."— Presentation transcript:

1 Computing Machinery Chapter 7: Register Transfers

2 A Register Transfer

3 Immediate and Direct Register Transfer Modes Immediate Mode - In the immediate mode, a literal data value (constant) is loaded into memory or a register. For instance, the value 1234 is loaded into register R Direct Addressing Mode - In direct addressing mode, the value on the right-hand side (rhs) of the register transfer refers to the address (location) in memory of the value being loading into the register. The value at memory address 1234 is loaded into R alternatively the data in register R is transferred to Memory address 1234 by,

4 Register Indirect Addressing - We can also refer to an address as a variable such as in another register. In this example, the contents of memory at an address stored in register R2 is loaded into register R1, Register Addressing Modes One of the applications made simpler by this addressing mode is stepping through an array of values stored in a contiguous region of memory. where the second register transfer refers to incrementing the value contained in R2. The third register transfer could be replaced with a loop back to the first register transfer using an algorithmic state machine model.

5 Indexed Addressing Mode - In this data transfer mode, the address in memory is determined by a combination of the contents of a register and a constant value. Indexed Transfer Modes The address of the value loaded into R1 is the contents of R2 plus the value 1234. In this example, we may be referring to the 1234th element of an array of values in memory starting at address R2. Indirect Addressing - Also called memory indirect addressing, this mode uses one value in memory as an address to locate the address of another value in memory. Load into R1 the value located in memory at the address stored in memory at address 1234,

6 Operations on Registers ADD R1, R2, R3 Three-Register Operations Two-Register Operations Single-Register Operations Assembly Register Transfer Operation ADD R1, R2 Assembly Register Transfer Operation ADD R Assembly Register Transfer Operation

7 LDA R3 load ACC with the value in R3 ADD R2 add the value of R2 to the value in ACC STA R1 store the value in ACC into R1 Register Operations and Assembly Instructions

8 Basic Arithmetic Operations n-bit left shift n-bit right shift

9 Logical Operations Addr Class Bits for Subnet Mask Subnet Mask. Class A 11111111 00000000 00000000 00000000 255. 0. 0. 0 Class B 11111111 11111111 00000000 00000000 255.255. 0. 0 Class C 11111111 11111111 11111111 00000000 255.255.255. 0

10 Conditional Operations

11 Algorithmic state machines are less formal than FSMs and are easier to understand. They are like flowcharts with a few added rules and restrictions. Their principal value is as an alternative to FSMs for designing sequential circuits. Algorithmic State Machine Rami Abielmona, Advanced Topic Lecture #3, ASM Design, SMRLab – SITE – University of Ottawa, CEG 3151 – High Level Computer Systems Design, May 21, 2003

12 Step 1: Algorithm Description - Create an algorithm that describes the operation of the circuit being designed. Step 2: ASM Chart - Convert the algorithm into a graphical representation. Step 3: Datapath - Design a datapath based on the ASM chart. Step 4: Detailed ASM Chart - Use the datapath to complete the ASM chart. Step 5: Control Logic - Design the control logic based on the detailed ASM chart. ASM Design Process

13 section_0 A ← Input1; B ← Input2; Count ← Input3; count_loop if (Count > 0) (goto section_1); else (goto section_2); section_1 A ← A + B; Count ← Count - 1; (goto count_loop); section_2 If (A > 25) Output ← A; (goto section_2); Algorithm Description Rami Abielmona, Advanced Topic Lecture #3, ASM Design, SMRLab – SITE – University of Ottawa, CEG 3151 – High Level Computer Systems Design, May 21, 2003

14 ASM Chart Rami Abielmona, Advanced Topic Lecture #3, ASM Design, SMRLab – SITE – University of Ottawa, CEG 3151 – High Level Computer Systems Design, May 21, 2003

15 Just as the ASM chart shows the flow of control signals, the datapath emphasizes the flow of data. The datapath diagram displays each register (and other memory elements), their inputs, outputs, and operations on them in order of execution. Datapath

16 The Detailed ASM Chart includes the control signals and conditionals defined in the datapath in our ASM chart. In building the detailed ASM chart, we need to follow certain rules and protocols: Detailed ASM Chart

17 ASM Component to Circuit Conversion

18 Conversion Transformation Process Ali Tehrani, A Systematic Approach to Logic Design, Chapter 4, Conestoga College Electronics Engineering Technology, Reconfigurable Computing, Course Notes, Winter 2005.

19 "One-Hot" Circuit

20 Summary Register Transfers define the operations of computing hardware circuits that move data instructions between memory, ALU and registers. The ad-hoc sequential design methods we have covered in Chapter 5 of the textbook can be codified into a formal procedure. There are a number of proprietary design tools that are based on ASMs such as Verilog, and VHDL (Very High Definition Language) but these tools are not necessary to use ASMs effectively. There are many excellent books and other references for ASMs.

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