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7-5 Microoperation An elementary operations performed on data stored in registers or in memory. Transfer Arithmetic Logic: perform bit manipulation on.

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Presentation on theme: "7-5 Microoperation An elementary operations performed on data stored in registers or in memory. Transfer Arithmetic Logic: perform bit manipulation on."— Presentation transcript:

1 7-5 Microoperation An elementary operations performed on data stored in registers or in memory. Transfer Arithmetic Logic: perform bit manipulation on data in register Bitwise AND, Bitwise OR …. Shift

2 Arithmetic Microoperations

3 The control variable X selects the operation, and the control variable K1 loads the result in to R1. Fig. 7.6 Implementation

4 Logic Microoperations manipulate the bits stored in a register consider each bit in register separately

5 Logic Microoperations Mask: allow us to deal with some specific bits R1: (data) R2: (mask) <= R1 ←R1^R2

6 Logic Microoperations R1: (data) R2: (mask) <= R1 ←R1ˇR2 R1: (data) R2: (mask) <= R1 ←R1 R2

7 Shift Microoperations shift left/shift right incoming bit/outgoing bit

8 7-6 Microoperation on A single Register Multiplexer-based transfer if (K1=1) then (R0 ← R1 ) else if (K2=1) then (R0 ← R2 ) K1: R0 ← R1, R0 ← R2

9 Multiplexer-based transfer

10 Generalization of Multiplexer selection for n sources

11 Shift Registers Serial input (SI) Serial output (SO)

12 Shift Register with parallel load

13 Shift Register with Parallel Load

14 Bidirectional Shift Register One stage diagram

15 Bidirectional Shift Register

16 Ripple counter Structure similar to ripple adder

17 Synchronous Binary Counter -Serial gating

18 Synchronous Binary Counter -Parallel gating Only one AND gate delay Four AND gates delay

19 Up-Down Binary Counter Homework #1 Prove it and draw the logic diagram S=0 up counter S=1 down counter

20 Binary counter with parallel load Fig It is a case of the up-down counter in the previous slide. (why? what case?)

21 BCD counter A divide-by-N counter (modulo-N counter) is a counter goes through a repeated sequence of N states Fig. 7-15

22 Another BCD counter

23 Modulo 6 counter

24

25 Homework #2 Problem 7-15 with modified sequence 0,3,2,1,5,4,7 Run the simulation for the designed circuit by using Quartus II Deal with the unused state as don’t care Test the circuit when the unused state occurs (on paper)


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