Presentation on theme: "ENGS 116 Lecture 111 ILP: Software Approaches 2 Vincent H. Berk October 14 th Reading for monday: 3.10 – 3.15, 4.7 - 4.11 Reading for today: 4.2 – 4.6."— Presentation transcript:
ENGS 116 Lecture 111 ILP: Software Approaches 2 Vincent H. Berk October 14 th Reading for monday: 3.10 – 3.15, Reading for today: 4.2 – 4.6 Homework #2 due now.
ENGS 116 Lecture 112 Trace Scheduling Focus on critical path (trace selection) –Compiler has to decide what the critical path (the trace) is –Most likely basic blocks are put in the trace –Loops are unrolled in the trace Now speed it up (trace compaction) –Focus on limiting instruction count –Branches are seen as jumps into or out of the trace Problem: –Significant overhead for parts that are not in the trace –Unclear if it is feasible in practice
ENGS 116 Lecture 113 Superblocks Similar to Trace Scheduling but: –Single entrance, multiple exits Tail duplication: –Handle cases that exited the superblock –Residual loop handling –Could in itself be a superblock Problem: –Code size –Worth the hassle?
ENGS 116 Lecture 114
5 Conditional instructions Instruction that is executed depending on one of its arguments: Instruction is executed but results are not always written. Should only be used for very small sequences, else use normal branch. BNEZ R1, L ADDU R2, R3, R0 L: CMOVZ R2, R3, R1
ENGS 116 Lecture 116 Speculation Compiler moves instructions before branch if: –Data flow is not affected (optionally with use of renaming) –Preserve exception behavior –Avoid load/store address conflicts (no renaming for memory loc.) Preserving exception behavior –Mechanism to indicate an instruction is speculative –Poison bit: raise exception when value is used –Using Conditional instructions: Requires In-Order instruction commit Register renaming Writeback at commit Forwarding Raise exceptions at commit
ENGS 116 Lecture 117 Speculation if (A==0) A=B; else A=A+4; LDR1, 0(R3); load A BNEZR1, L1; test A LDR1, 0(R2); then JL2; skip else L1:DADDIR1, R1, #4; else L2:SDR1, 0(R3); store A LDR1, 0(R3); load A LDR14, 0(R2); load B (speculative) BEQZR1, L3; branch if DADDIR14, R1, #4; else L3:SDR14, 0(R3); store A