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234262 – © Yohai Devir 2007 Technion - IIT 234262 Tutorial #10 MIPS commands.

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Presentation on theme: "234262 – © Yohai Devir 2007 Technion - IIT 234262 Tutorial #10 MIPS commands."— Presentation transcript:

1 – © Yohai Devir 2007 Technion - IIT Tutorial #10 MIPS commands

2 – © Yohai Devir 2007 Technion - IIT MIPS overview MIPS is a simple processor: All arithmetic operations are done with registers only. Memory access is done with only two instructions – LOAD \ STORE. The MIPS is a 32-bit machine. The instructions are 32-bits long. Register file (RF), with 32 registers of 32 bits each (5 bit for the number) Memory address size – 32 bits. We’ll work in resolution of words – 32bit each.

3 – © Yohai Devir 2007 Technion - IIT Registers There are registers which are denoted by R0, R1,…R31. Register 0 is read-only and its value is 0 (R0 ≡ 0). The PC (Program Counter) is a special register. The PC points to the next instruction to be executed. In some places register K is marked as $K (i.e. R8 ≡ $8)

4 – © Yohai Devir 2007 Technion - IIT Memory (maximal) size 2 30 words of 32 bits each. Each word has a 32-bit address, the two LSB bits of the address are 00. Memory is accessed only by LOAD\STORE commands

5 – © Yohai Devir 2007 Technion - IIT Instructions 3 types of instructions, each kind with a fixed structure: Type R (Register) Type I (Immediate) Type J (Jump)

6 – © Yohai Devir 2007 Technion - IIT Type R OPeration Source \ Target \ Destination Register SHift AMounT FUNCtion OPRsRtRdshamtfunc 6 bit5 bit 6 bit

7 – © Yohai Devir 2007 Technion - IIT ADD R11,R20,R3 Semantic: R11  R20 + R3 Performs addition of the values of R20 and R3 and stores the result in R11 OPRsRtRdshamtfunc 0 6 bit5 bit 6 bit

8 – © Yohai Devir 2007 Technion - IIT ADD R11,R20,R3 Semantic: R11  R20 + R3 OPRsRtRdshamtfunc bit5 bit 6 bit

9 – © Yohai Devir 2007 Technion - IIT ADD R11,R20,R3 Semantic: R11  R20 + R3 OPRsRtRdshamtfunc bit5 bit 6 bit

10 – © Yohai Devir 2007 Technion - IIT ADD R11,R20,R3 Semantic: R11  R20 + R3 OPRsRtRdshamtfunc bit5 bit 6 bit

11 – © Yohai Devir 2007 Technion - IIT ADD R11,R20,R3 Semantic: R11  R20 + R3 OPRsRtRdshamtfunc bit5 bit 6 bit OPRsRtRdshamtfunc bit5 bit 6 bit

12 – © Yohai Devir 2007 Technion - IIT OR R8,R7,R6 Semantic: R8  R7 OR R6 Performs bitwise logical OR between the values of R7 and R6 and stores the result in R8 OPRsRtRdshamtfunc bit5 bit 6 bit

13 – © Yohai Devir 2007 Technion - IIT SLT R10,R20,R30 Semantic: If (R20 < R30) R10  000… …00001 (32bit) else R10  000… …00000 (32bit) Name: Set Less Than OPRsRtRdshamtfunc bit5 bit 6 bit

14 – © Yohai Devir 2007 Technion - IIT SLL R5,R7,2 Semantic: R5  R7 << 2 Name: Shift Left Logical Example: if R7= 11100… …01111 then R5 = 100… … SRL does the same but shifts right OPRsRtRdshamtfunc Not bit5 bit 6 bit

15 – © Yohai Devir 2007 Technion - IIT Type I OPeration Source \ Target Registers IMmediate OPRsRtIM 6 bit5 bit 16 bit

16 – © Yohai Devir 2007 Technion - IIT ADDI R2,R29,144 Semantic: R2  R Bigger constants? OPRsRtIM bit5 bit 16 bit OPRsRtIM bit5 bit 16 bit

17 – © Yohai Devir 2007 Technion - IIT LUI R3,0xB3A0 Load Upper Immediate Semantic: 1.Sets the 16 MSBs of R3 to 0xB3A0 2.Zero the 16 LSBs of R3 OPRsRtIM 15030xB3A0 6 bit5 bit 16 bit

18 – © Yohai Devir 2007 Technion - IIT LUI Example: In order to load 0x2AC0900 to R3: R3 (before) = 0x ABCD 1234 LUI R3, 0x02AC R3 = 0x 02AC 0000 ADDI R3, 0x0900 R3 = 0x 02AC 0900

19 – © Yohai Devir 2007 Technion - IIT BNE R31,R8,loop1 Branch on Not Equal Semantic: if R31!=R8, the next instruction to be executed is the on which is stored in the memory at label ‘loop1’ BEQ branches if EQual OPRsRtIM 4318? 6 bit5 bit 16 bit

20 – © Yohai Devir 2007 Technion - IIT BNE R31,R8,loop1 labelAddress (decimal) instruction gremlin:00…000984ADDI R5,R0,81 00…000988SUB R7,R9,R12 00…000992… 00…000996ADDI R1,R0,5 Loop1:00…001000ADD R1,R1,R3 00…001004… … 00…001016SUBI, R1,R1,1 00…001020BNE R1,R0,loop1

21 – © Yohai Devir 2007 Technion - IIT (BNE addr ) BNE We want to branch to address 00… However, this a 32bit address while having only 16bit of IM. Most branches are to “nearby” addresses.  We can put address relative to the PC. 2 LSB bits are ’00 (Why?)  No need to specify the 2 LSBs. We’ll see this later: After bringing the intruction (before really reading it) the PC is incremented in 4 bytes. PC new  (BNE addr +4)+IMx4

22 – © Yohai Devir 2007 Technion - IIT BNE R31,R8,loop1 Loop1:00…001000ADD R1,R1,R3 … 00…001020BNE R1,R0,loop1 BNE instruction address is 1020, branch address is After fetching the instruction the PC will be 1024   we need to branch to an address - 24 bytes away. No need to store the 2 LSBs  (-24)/4 = -6  IM should be -6 OPRsRtIM bit5 bit 16 bit

23 – © Yohai Devir 2007 Technion - IIT LW R2,100(R3) Load Word Semantic: Read the word located in the memory address of [R3] (not 103 !!!) and write it to R2 NOTE: Rs is the Base register Rt is the register to write to. OPRsRtIM bit5 bit 16 bit

24 – © Yohai Devir 2007 Technion - IIT SW R7,200(R6) Load Word Semantic: Writes the word located in R7 to the memory address of [R6] (not 206!!!) NOTE: Rs is the Base register Rt is the read from. OPRsRtIM bit5 bit 16 bit

25 – © Yohai Devir 2007 Technion - IIT Type J OPeration eXtended Immediate Unconditional jump 2 LSBs are ’00. No need to specify them. 4 MSBs are taken from PC OPXI 6 bit26 bits

26 – © Yohai Devir 2007 Technion - IIT J 0xEF Jumps to a specific address Semantic: PC new  PC [upper 4 MSBs] || XI || 00 OPXI 2? 6 bit26 bits

27 – © Yohai Devir 2007 Technion - IIT J 0xEF Example: 0xE in binary is: Without 4 MSBs and 2 LSBs: Back to Hex: Therefore XI = 0x3D Address (HEX)instruction 0x E :J 0xEF EF D11111

28 – © Yohai Devir 2007 Technion - IIT JAL 0xEF Jump And Link Stores PC in Register 31 and then jumps to given address. Semantic: R31  PC PC  PC [upper 4 MSBs] || XI || 00 OPXI 3? 6 bit26 bits

29 – © Yohai Devir 2007 Technion - IIT JR R17 Jump Register – a Type R command. Semantic: PC  R17 OPRsRtRdshamtfunc bit5 bit 6 bit


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