Download presentation

Presentation is loading. Please wait.

Published byTristan Shore Modified over 2 years ago

2
Pipeline Summary Try to put everything together for pipelines Before going onto caches. Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Dr. Leo Porter Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License

3
Given our 5-stage MIPS pipeline – what is the steady state CPI for the following code? Assume the branch is taken thousands of times. Recall – a processor is in steady state when all stages are active. Loop: lw r1, 0 (r2) add r2, r3, r4 sub r5, r1, r2 beq r5, $zero, Loop SelectionCPI A1 B1.25 C1.5 D1.75 ENone of the above Steady-State CPI = (#insts+#stalls+#flushed_insts) #insts

4
IF = 200ps ID = 100ps EX = 100ps M = 200ps WB = 100ps Hardware engineers determine these to be the execution times per stage of the MIPS 5-stage pipeline processor. Consider splitting IF and M into 2 stages each. (So IF1 IF2 and M1 M2.) The most important code run by the company is (assume branch is taken most of the time): Loop: lw r1, 0 (r2) add r2, r3, r4 sub r5, r1, r2 beq r5, $zero, Loop SelectionCPICT AIncrease B Decrease C Increase DDecrease EIncreaseNo Change What would be the impact of the new 7-stage pipeline compared to the original 5-stage MIPS pipeline.. Assume the pipeline has forwarding where available, predicts branch not taken, and resolves branches in ID.

5
IF = 200ps ID = 100ps EX = 200ps M = 200ps WB = 100ps Hardware engineers determine these to be the execution times per stage of the MIPS 5-stage pipeline processor. Consider splitting IF and M into 2 stages each. (So IF1 IF2 and M1 M2.) The most important code run by the company is (assume branch is taken most of the time): Loop: lw r1, 0 (r2) add r2, r3, r4 sub r5, r1, r2 beq r5, $zero, Loop SelectionCPICT AIncrease B Decrease C Increase DDecrease EIncreaseNo Change What would be the impact of the new 7-stage pipeline compared to the original 5-stage MIPS pipeline.. Assume the pipeline has forwarding where available, predicts branch not taken, and resolves branches in ID.

6
Loop: lw r1, 0 (r2) add r2, r3, r4 sub r5, r1, r2 beq r5, $zero, Loop 7-stage Pipeline

7
Pipelining -- Key Points Pipelining focuses on improving instruction throughput, not individual instruction latency. Data hazards can be handled by hardware or software – but most modern processors have hardware support for stalling and forwarding. Control hazards can be handled by hardware or software – but most modern processors use Branch Target Buffers and advanced dynamic branch prediction to reduce the hazard. ET = IC*CPI*CT

Similar presentations

OK

Comp Sci 251 -- pipelining 1 Ch. 13 Pipelining. Comp Sci 251 -- pipelining 2 Pipelining.

Comp Sci 251 -- pipelining 1 Ch. 13 Pipelining. Comp Sci 251 -- pipelining 2 Pipelining.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Slideshare download ppt on pollution Ppt on balancing redox reactions Ppt on media research center Ppt on economic systems Ppt on solid dielectrics inc Ppt on chapter 12 electricity and magnetism Ppt on network switching tutorial Ppt on economic order quantity example Ppt on internet addiction Urinary tract anatomy and physiology ppt on cells