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Group Number One GITHU Processor Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst.

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Presentation on theme: "Group Number One GITHU Processor Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst."— Presentation transcript:

1 Group Number One GITHU Processor Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst

2 GITHU Processor General Purpose 32-bit, pipelined computer processor MIPS-like architecture – Reduced instruction set 16-bit address space 16 Registers – R0 = 0 – R15 = return address

3 FPGA RAMROM Ribbon Cable Data/Address Ribbon Cable Level Shift Interrupt Controller / Chip Select Ribbon Cable Level Shift Key Pad LCD Monitor Out Keyboard In I/O UART Interrupt Data Ribbon Cable

4 Instruction Set Architecture First two bits indicate instruction category – Load, store, bra/jump, R-type 16 bit immediate built into R-type reduces complexity of design Addressing Modes – Direct – Indirect with Offset ISA accounts for full address space – NO PC-relative addressing

5 Instruction Format Op(2)Addr(6)Rt (4)Rs (4)Address Displacement (16) Op(2)Type(4)Addr (2)Rs (4)Address Continued (20) Load / Store R-Type Bra / Jmp Op (2)Funct (5)Imm (1)Rd (4)Rs1 (4)Rs2 (4)Immediate (12)

6 Load/Store Instructions (Op = 00/01) InstructionAssemblyMeaning LdLd 0[r3], r2 R2  Mem(r3) StSt r4, 4[r3] R4  Mem(r3 + 4)

7 R-Type Instructions (OP = 10) InstructionFunctionImmedAssembly ExMeaning (** = bitwise op) Add000000Add r2, r3, r4R2 = R3 + R4 Addi000001Addi r2, r2, 5R2 = R2 + 5 Sub000010Sub r6, r3, r5R6 = R3 – R5 Subi000011Subi r3, r4, 3R3 = R4 – 3 And001000And r3, r2, r8R3 = R2 & R8 ** Andi001001Andi r4, r4, 255R4 = R4 & 0xFF ** Or001100Or r2, r3, r4R2 = R3 | R4 ** Ori001101Ori r2, r8, 10R2 = R8 | 0xA ** Nand001010Nand r3, r5, r9R3 = !(R5 & R9) ** Nor001110Nor r2, r1, r4R2 = !(R1 | R4) ** Xor100100Xor r3, r4, r5R3 = R4 ! R5 Mult110000Mult r2, r3, r4R2 = R3 * R4 Div111000Div r4, r5, r2R4 = R5 / R2

8 R-Type Instructions (Cont’d) InstructionFunctionImmedAssembly ExMeaning (** = bitwise op) Sll010000Sll r2, r2, r3R2 = [R2] << R3 Slr010010Slr r2, r2, r3R2 = [R2] >> R3 Sal010100Sal r4, r4, r3R2 = [R4] << R3 Sar010110Sar r4, r4, r3R2 = [R4] >> R3 Scl011000Scl r4, r4, 1Circular shift left Scr011010Scr r3, r3, 1Circular shift right Slt100000Slt r2, r3, r4R2 =1 IF R3

9 Bra/Jmp Instructions (Op = 11) InstructionTypeAssemblyMeaning Beq0001Beq r2, loopIF r2 == 0, go to loop Bne0010Bne r3, loopIF r3 != 0, go to loop Jmp0100Jmp mainJump to “main” Jpr0110Jpr r3Jmp to addr. In r3 Jsr1000Jsr subJump to sub, save PC

10 Hardware

11 Data Path Diagram

12 RAM – Read Access

13 RAM – Write Access

14 ROM – Timing Diagram

15 LCD – Display Timing

16 Parts List ItemQuantity Xilinx XCV400 FPGA (Virtex)1 Flash Memory2 SRAM1 Perf Board1 Level Shifters5 Ribbon Cable (and headers)4 Dip Sockets8 4 x 20 LCD screen1 16 button Keypad1

17 Remaining Individuals Roles Tom Bozic – Control logic, documentation, Interrupt Controller Ian Nuber – Maintain Assembler, Interrupt handler, program design Greg Ramsey – Memory system design (RAM, ROM), PCB design Henry Romero – PCB design, peripheral integration Matt Unangst – Pipeline implementation (forwarding, rollback) – Design integration oversight

18 Milestone 1 Pipeline implemented – Thoroughly tested First PCB rev completed Successful integration of processor, I/O, Memory Test program(s) written User’s Manual near completion

19 Milestone 2 FINAL PRODUCT COMPLETE – Allows room for unexpected errors Forwarding Path’s implemented in pipeline Final PCB rev completed, implemented Full integration of processor, I/O, memory Demo program completed Complete documentation

20 Schedule

21 Questions?

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