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Published byMario Bagshaw Modified over 3 years ago

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Mihai Albulet 윤석현

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A class D amplifier is a switching-mode amplifier that uses two active device driven in a way that they are alternately switched ON and OFF. The Active device form a two-pole switch that define either a rectangular voltage or rectangular current waveform at the input of a tuned circuit that includes the load.

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Complementary Voltage Switching (CVS) Circuit Q1 and Q2 switch alternately Between cut-off(off state) And saturation ( on state)

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1. The CVS circuit requires a series-tuned circuit or an equivalent (that imposes a sinusoidal current), such as a T- network. 2. The active devices act ideal switches 3. The active devices have null output capacitnace 4. All component are ideal. (the possible parasitic resistance of L and C can be included in the load resistance R;)

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Assuming a 50 percent duty cycle ( that is, 180 degree of saturation and 180 degree of cutoff for each transistor)

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At one moment, the sinusoidal output current flows through either Q1 or Q2, depending on which device is ON. As a result, collector currents and are half sinusoidal with amplitude The output power

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The current drawn from the DC power supply take the form of a half sinusoidal pulse train; therefore, a local bypass capacitor is required. In practice, the use of an additional filter in the power supply line is recommended ( see Fig 3-3) -> C1, C2 C2 must be able to store enough energy to supply the required current pulses without a significant voltage drop in the Q1 collector.

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As in the CVS circuit, input transformer T1 allow Q1 and Q2 to switch ON and OFF. The circuit analysis is based on the simplifier assumptions provided in section complementary Voltage Switching (CVS) circuit ; For if Q2 is ON and Q1 is OFF. Consequently for For Q1 is ON and Q2 is OFF Consequently for,

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Input transformer T1 determines that Q1 and Q2 will switch alternately ON and OF (a 50 percent duty cycle is assumed). The following analysis is based on the simplifier assumptions provided in section Complementary Voltage Switching (CVS) Circuit, with one exception. The TCCS circuit requires a parallel resonant circuit instead of a series resonant type.

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The RF choke forces input current Idc into the center tap of the primary winding. This current is directed to ground through the active device that is in the ON state. AS a result, collector currents and are square waves with levels of 0 and Idc ( see Fig 3-9) Transformation of these current in the secondary winding of T2 determines a square-wave current.

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For, suppose that Q2 is ON and Q1 is OFF, yielding Because the voltage across the secondary winding is sinusoidal, the voltage across each half of the primary winding is also sinusoidal For Q1 is ON and Q2 is OFF. Thus,

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Finally, note that TCCS circuit is the “dual” of the TCVS circuit, because the voltage and current waveforms are interchanged.

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In practical circuit, the simplifier assumptions given in section complementary voltage switching (CVS) circuit usually connot be accepted. 1. The real transistor have nonzero switching times, parasitic inductance and capacitances, nonzero ON resistance and, possibly, a saturation voltage. 2. The capacitor and inductor from the output-tuned circuit have parasitic resistances( that is unloaded quality factor). 3. The output-tuned RLC circuit has a finite-loaded quality factor

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4. The load circuit can have a nonzero net reactance at the operating frequency caused by mistuning, for example. 5. It is possible for frequency variation or change to appear in the transistor’s timing.

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As a jumping off point, consider a CVS Class D circuit with a reactive load. (see Fig 3-11) The series net reactance X (at the switching frequency f) can model a circuit mistuning or a change of the operating frequency.

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Because of the series reactance, the output current (and the output voltage ) is phase shifted relative to the voltage waveform, and both and are negative during a portion of each period. If Q1 and Q2 are BJTs, the negative current (which can not pass through the transistor) charge capacitance Cp1 and Cp2, producting large voltage spikes that can damage the transistors.

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A suitable path for the negative collector current is provided by diodes D1 and D2 in Fig 3-13.

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Note that the current pulse through Q1 and Q2, which charge/discharge Cp1 and Cp2 when switching occurs, are shown for accuracy in Fig 3-12 and 3-14.

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Linear output capacitance The parasitic capacitance shunting an active device (Cp1 and Cp2, Fig 3-11) include the output capacitance of the transistor and the stray capacitance.

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If Q1 is ON and Q2 is OFF, then Cp1 is discharged and Cp2 is charged to Vdc. When Q1 turns OFF and Q2 turns ON, Cp2 is discharged instantaneously through the zero ON resistance of Q2. Cp1 is charged (also instantaneously through Q2) to Vdc. When Cp2 is discharged, the energy stored in it is dissipated( in Q2)

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Simultaneously, energy is dissipated (also in Q2) to charge Cp1 from zero to Vdc. When Q1 turns ON and Q2 turns OFF, Cp2 is charged to Vdc and Cp1 is discharged

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1.The power loss due to this mechanism do not cause a decrease of output power. This is because the current that charge and discharge capacitance Cp1 and Cp2 flow only through Q1, Q2, and the power supply, and do not circulate through the load 2. In a real amplifier, the charge or discharge of a parasitic capacitance requires a nonzero length of time, during which the collector voltage and current are simultaneously nonzero. 3.If Q1 and Q2 are bipolar transistor, the parasitic capacitance are charged and discharged between Vdc and Vdcsat.

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4. Power loss increase with the parasitic capacitance Cp, the switching frequency f, and the square of the DC supply voltage Vdc. These loss limit the usability of the Class D power amplifier at high frequencies.

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In the TCVS class D circuit, the parasitic capacitance of Q1 and Q2 are charged and discharged between 0 and 2 Vdc (see Fig 3-7)

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The charge/discharge losses in the TCVS circuit are four times greater than the losses in the CVS circuit, for the same Cp, Vdc and f. The charge/discharge losses are the same for both Class D circuit. In the TCVS, only one half of power loss is dissipated in Q1 and Q2. This is because parasitic capacitances Cp1 and Cp2 are charged Through the primary winding of the output transformer and are only discharged through Q1 and Q2.

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Most of the parasitic capacitance, Cp (in both BJTs and MOSFETs amplifiers) is an abrupt-junction capacitance.

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In the TCCS class D circuit, the parasitic capacitance do not have charge/discharge losses due to the mechanism described. However, in the TCCS circuit, there is another power loss mechanism. The currents through the active device jump when switching occur(fig 3-9), and this causes losses due to series inductances at the switch.

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1. The CVS circuit appears to have disadvantage in comparison with the TCVS circuit. 2. If TCVS circuit operates at half the supply voltage used by a CVS circuit, the output power and the transistor rating are the same for both configurations. In case the power loss due to the parasitic capacitance are the same in both circuit and the effects of Vcesat on the circuit performance.

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During saturation, bipolar transistor are characterized by a roughly constant saturation voltage, Vce sat, and a roughly constant saturation resistance, Rce sat Field-effect transistors are characterized ( during ON state) by a roughly constant drain-to-source resistance, RDS,ON. Generally, the active device ON resistance is donated below by Ron.

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All class D configuration, it is obvious that the waveform are affected by the nonzero ON resistance R ON.

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