South Arm West East Noisy ADTX Check Grounding Noisy ADTX Check Grounding Station-2,3 9 11137,11138 S3 O5 C2 11064 S2 O3 C4 11134 S3 O4 C5 HV St3, Oct1 S311-0 (couldn’t fix) HV St3, Oct7 S371-6 (couldn’t fix)
MuTr RX Card Debugging (1) RX card transmits electrical signal to optical. We have only 3 spare good boards and 7 spare boards to be debugged. To be tested at John Haggerty’s test bench. 10 MUTR FEE RX card DCM opticalelectrical
MuTr fiber labeling Redo MuTr fiber labeling at DCM. The new label suppose to have Module# and dsp# as well. 12
Debugging MRG FPGA Symptom South Octant-1Constant Rates (Threshold dependent) South Octant-3Excursion w/ time constant of ~20minutes North South Run12 Octant-1 Cosmic SG1~50kHz Run12 Octant-1 Physcs SG1~1kHz Plot by Dahee (Ewha University) South Octant-3 Above two octants are running with older version of MRG FPGA in Run13. Both are observable with cosmic circumstances FPGA: verilog HDL 13
Summary So far high rates in both Oct-1 and Oct-3 are both disappears with down graded MRG FPGA code. Whether we run with mixed two FPGA code? Down grade all octants? Confirm stability using cosmic as long as possible. 16
When did this started? 17 FPGA Upgrade (Mar. 28, 2012) FPGA Upgrade (Mar. 28, 2012) - runtype: CALIBRATION data - triggerconfig: PP510Run12_Cosmic - run time > 10 min - MUIDLL1_N1D||S_1D trigger enabled. 40kHz S_SG1 rate Octant-3 Threshold=20mV for Cosmic Runs. Run Rate[kHz]
Run13 Threshold Response of Octant-1 North South Run12 Octant-1 Cosmic SG1~50kHz Run12 Octant-1 Physcs SG1~1kHz Plot by Dahee (Ewha University) 18 Run12 Cosmic Rate ~40kHz is consistent with present measurement. Physics run was operated at 30mV and likely to be operated around 1kHz.
Time dependent rate in Run12 Cosmic 19 mrg_prom021 mrg_prom036 S_SG1 Rate No indication of Oct-3 High rate excursion. Hidden under Oct-1 40kHz? Need Time dependent LL1SG1 rate Oct-by-Oct -> Josh developed in the past?
Octant-1 Diagnosis Station-1, Station-2 Mask Station-3b (done) Chip scope measurement using LL1 fire as trigger of chip scope Check the communication between MRG and LL1. How we know the communication error? Check the timing alignment error. Play with delay scan level-1 internal clock.(require LL1 FPGA modification) Perform MRG (process) delay scan (all stations at once) more precisely (to find the timing when LL1 started to fail align), 21
North Arm WestEast Station-1 Noisy ADTX Check grounding Noisy ADTX Check grounding Station-2,3 22 Need to change FEE boards 11300 S3 O2 C6
South Arm West East Noisy ADTX Check Grounding Noisy ADTX Check Grounding Station-2,3 23