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©2009 DJ Foreman CS552 Operating Systems z/390 Basic Assembler Language Programming.

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Presentation on theme: "©2009 DJ Foreman CS552 Operating Systems z/390 Basic Assembler Language Programming."— Presentation transcript:

1 ©2009 DJ Foreman CS552 Operating Systems z/390 Basic Assembler Language Programming

2 ©2009 DJ Foreman Architectures CISC Complex Instruction Set Computer –Multiple operands per instruction –Multiple instruction formats –64 bit architecture, Instr set is variable –32-bit –64-bit 32 bit instructions work on low-order RISC – Reduced Instruction Set Computer –One (expressly written) operand per instruction –Accumulator is 2 nd (implied) operand

3 Example 1: C=A+B; CISC (mainframe) LOAD5,A ADD5,B ST5,C RISC (PC) LOADA ADDB STC ©2009 DJ Foreman RISC becomes MUCH more complicated if A, B & C are subscripted. CISC is easier, because CISC instructions can have subscript in an “index” register.

4 Example 2: A=B; A & B are strings 1<=length<=256 MVCA(250),BSet -> A[0] Set -> B[0] Load index with max length of A Load*A Store*B Increment pointers Repeat 249 times ©2009 DJ Foreman Loop until max index

5 Elements of a machine -1 Registers –Numbered hardware location (NOT memory) –Used for Addressing (like a pointer in C) Arithmetic(just a simple accumulator) –Number of registers varies with architecture –Size varies: 32, 64 or 128 bits –ALL registers may be accumulators Stack –A set of registers accessed in LIFO order ©2009 DJ Foreman

6 Elements of a machine -2 Memory –Linear set of addresses –Accessible to a program Devices –Mechanical objects –Accessible Directly by device number for assembler programs Via special functions (e.g.; > in C++) Through a “device driver” ©2009 DJ Foreman

7 What is Assembler Language? Short names for native machine codes Saves memorizing hexadecimal values One name generates one instruction E.g. for a pretend machine; –Lx Loads the accumulator from memory “x” “x” defined by programmer as a variable –L15,X Loads register 15 from location “X” ©2009 DJ Foreman

8 I/O & State Subchannels –Allow for variability of h/w path to device –Use a "control block" for access Program Status Word –Interruptability (on/off) –Privilege mode (on/off) –Wait state (on/off) –Next instruction

9 ©2009 DJ Foreman Instruction Format Terms Opoperation code (8 bits) R1, etc.register number 0-F (8 bits) Bregister used as address base Xregister used as an index DDD0-FFF 12-bit disp. from base M,I8-bit mask or immediate data LLlength of data (256 bytes max)

10 ©2009 DJ Foreman z/390 Instruction Architecture Most-used formats

11 Instruction formats Following slides show each format 2 ways: –Actual memory arrangement As seen in a memory dump –As written (with data names) in a program LR1,mydata(R2) Known as: “Base-Displacement” notation BE CAREFUL, SYNTAX CAN BE CONFUSING! ©2009 DJ Foreman OpR1R1 R2R2 BDDD

12 Hexadecimal equivalent –As written (with code) in a program LR1,DDD(R2,B) shown in some following slides Note that no actual data names are used in this version Same instruction example with real numbers –L12,x’05e’(3,4) Add contents of reg’s 3 and 4 to displacement (5e) to get the actual address of data being loaded Note: no 0 in front of the x, quotes used instead ©2009 DJ Foreman

13 Notation tricks The assembler program (the “compiler”) allows “substitutions” for numbers via an “EQU” instruction (really a “directive”) Examples: –R5EQU5 –XYZEQUX’5E’ –DJEQU4095(max value) Allows writing –LR5,XYZ(3,4) vs. L5,X’4E’(3,4) –Just easier to write, no advantage in code ©2009 DJ Foreman

14 Base Register Specification USINGTells assembler which register to use for names –Register to use as Base –Generates NO code (takes no space in memory) Example: BALR12,0puts addr of "go“ into R12 USING*,12 goMVCData1(5),Data2 Data1DCC'target location' Data2DCC'Source' Data1 is 6 bytes from "go" –The * means: "starting here" and the MVC is 6 bytes long –Could have said: USING go,12 If Reg 12 has address of "go", then data1 is 6 bytes from Reg 12 YOU must put the correct memory address into the Base Reg DROPterminates use of a register for name addressability

15 ©2009 DJ Foreman RR Format Example: AR5,14 –Operation code is 1A –Adds the contents of Reg 14 to the contents of Reg 5 –results in Reg 5 –No memory references involved Note: examples show Regs as decimal values, but Assembler converts them to Hexadecimal In memory, this instruction looks like: 1A5E OpR1R2

16 Memory address is: – content of X –+ content of B –+ value DDD Example: –LLoad – Operation code X'58' –LR,DDD(B,X) –L4,mydata(12) Result replaces value in R –If "mydata" is at offset X'23' from Reg 5, which holds X'0E00', then, in memory, this will look like: 584C5023 –Mydata becomes a "starting point, and the content of Reg 12 is added to it as an "index" - nice for table accesses ©2009 DJ Foreman RX Format OpRXBDDD + Arrows reverse for store operations

17 ©2009 DJ Foreman RS Format Memory address: –content of B –+ value DDD Example: –LMLoad Multiple - Opcode X'98' –LMR 1,R 2,DDD(B) –LM4,7,mydata Result: Loads all registers from R 1 to R 2, from data at "mydata" –If "mydata" is at offset X'23' from Reg 5, which holds X'0E00', then, in memory, this will look like: –Note: "wrap-around" of register numbers is legal Ex: LM 14,12 loads regs 14, 15, 0,1,2,…,12 inclusive OpR1R1 R2R2 BDDD Arrows reverse for store operations

18 ©2009 DJ Foreman SI Format Performs "Op" using the instruction content itself (Imm) as data. That is, no additional memory reference is done.) Example: –NAnd Immediate - Opcode X'94' –NDDD(B),I –Nmydata,X'0A' If "mydata" is at offset X'23' from Reg 5, which holds X'0E00', then, in memory, this will look like: 940A5023 Note: when writing the instruction, the memory ref comes 1 st, FOLLOWED BY the Imm data! OpImmBDDD

19 ©2009 DJ Foreman SS Format Memory address is: –+ content of B n –+ value DDD n Example: –MVC Move Characters - Opcode X'D2' –MVCDDD 1 (B 1,LL),DDD 2 (B 2 ) –MVCyourdata(23),mydata23=X'17' Result replaces value in B 1 DDD 1 –"mydata" is at offset X'02' from Reg 5 (X'0E00') –"yourdata" is at offset X'55' from Reg 8 (X'1F00') –then, in memory, this will look like: – D OpLLB 1 DDD 1 B 2 DDD 2

20 Additions A “word” is 32-bits, so a halfword is 16 bits Load and Store and math instructions can thus be used on 16-bit data, by appending the letter “H” to the opcode: –LHload halfword –STHstore halfword –AHadd halfword Results use low order half of register All registers are AT LEAST 32 bits ©2009 DJ Foreman

21 Writing a Program Assembler directives

22 ©2009 DJ Foreman Module Definitions CSECT - externally known module –Named or unnamed –Linkable object Could be a compilation result Contains program code or data DSECT - externally known "dummy" module –Used to define offsets –Like a "C" 'struct‘, requires a pointer Both ended by another C/DSECT or END

23 ©2009 DJ Foreman Storage Specification DCDefine Constant –Hex, character, decimal formats –Contains the actual "constants" –Constants are NOT protected DSDefine Storage –Allows for "reserving" an area –No pre-defined value, NOT zeroed out!!!

24 ©2009 DJ Foreman Storage Specification 2 Op[m] {attrib1} [Ln] 'value1‘note: quote signs Op[m] {attrib2} [Ln] (value2)note: parentheses –m is a repetition factor (0 is valid) –n is a length (per element) Attrib values –Attrib1X, C, H, F, D,B –Attrib2A, S Value1 is any hex, integer or character data Value2 is an address constant Examples DS0CL5uses no memory (so no quotes) DC3XL3'25' DCA(mydata)4-byte, aligned, address DCS(mydata)converts to base/disp notation

25 ©2009 DJ Foreman Setting a Base Address Special instruction:BALRR1,R2 At EXECUTION time, –R1 will receive the address of the NEXT inst in memory following the BALR itself –A branch (jump) will be taken to the address in R2 (call/return semantics) IF R2 is register 0, no branch is taken!!!

26 ©2009 DJ Foreman Naming EQU"equates" a name to a location or value Example: –Data1 DCX'010203'length attr=1 »Because no length was explicitly given –Data2 DCXL3'010203'length attr=3 –HextwoEQUData2+1 –K5EQU5 –Hextwo now refers to the offset* of 02 inside Data2 –BE CAREFUL: since the target of Hextwo is in a string of length 3, hextwo has a length 'attribute' = 3 –K5 has a numeric value of 5 - uses NO memory –* from the current USING directive’s address

27 ©2009 DJ Foreman Ending the Program Definition END –tells assembler "end of program" –Generates NO code. It is NOT a "return" Comments An * placed in column 1 of any line –tells assembler "ignore this line"

28 ©2009 DJ Foreman z/390 I/O

29 ©2009 DJ Foreman I/O Basic I/O instructions –SSCHStart Sub-Channel –TSCHTest " - clears pending interrupts Operand (SSCH/TSCH) points to an ORB –Control block –Specifies additional info for I/O system

30 ©2009 DJ Foreman ORB layout Word# Usage 0Interruption Parameter 1Key SCMYFPIAU0HT LPMLD00000X 2Channel-Program Address (address of 1st CCW in chain) 3CSS Priority ResCU priority Res 4-7Reserved

31 ©2009 DJ Foreman I/O Programming Setup the ORB Setup the interrupt handler Setup address of NSI in PSW to be loaded Setup low memory –(I/O new & PGM new PSW's) SSCH Enable interrupts Wait for interrupt

32 ©2009 DJ Foreman General Programming Concepts and Some IBM Specifics

33 ©2009 DJ Foreman IBM Application Conventions These do NOT apply to kernel code All APPLICATION programs return to caller via Reg 14 All programs save their caller's registers in an area pointed-to by Reg 13, STARTING WITH Reg 14 Example: –STM 14,12,12(13) saves callers regs 14, 15, 0,1, 2…12 in an area addressed by Reg 13+12

34 ©2009 DJ Foreman IBM Application conventions -2 Save Area Chaining USING*,15called via R15 MYPGSTM 14,12,12(13)save caller's regs ST13, mysave+4my save ->caller’s LR14,13ptr to caller's area LA13,mysave ST13,8(0,14)caller’s area->mine LA12,MYPGchange to R12 USING MYPG,12tell assembler    L13,MYSAVE+4restore caller regs LM14,12,12(13) BR14return to caller MYSAVE DS19Fspace for registers END

35 ©2009 DJ Foreman Macros Expand into actual inline code Save writing and remembering Allows for variable substitution Allows for different expansion, based on arguments –NOT a function call, –NOT a text substitution (as it is in C) It can generate DIFFERENT instructions oneach usage in a program

36 Example MACRO &LBL SETCTL &LBL STCTL C6,C6,SCRATCH MVI SCRATCH+4,X'FF' LCTL C6,C6,SCRATCH MEND ©2009 DJ Foreman So XYZSETCTL Generates: XYZSTCTLC6,C6,SCRATCH MVISCRATCH,X’FF LCTL C6,C6,SCRATCH Note: “SCRATCH” is 8 bytes

37 ©2009 DJ Foreman Kernel Programs

38 ©2009 DJ Foreman Structure Privileged No save-area chaining No "runtime" libraries Permitted access to ALL REAL memory Permitted access to REAL devices Two styles: –Monolithic - one complete linked file –Modular multiple files, dynamically loaded files

39 ©2009 DJ Foreman Context Management

40 ©2009 DJ Foreman Reserved Memory Page 0 is Reserved storage for kernel Accessible only in privileged mode Uses base register 0 (in CISC machines) – reg 0 is "treated" by hardware as if = zero, but CAN hold a number, which is ignored for addressing 4096 bytes (addresses 0-FFF) –Only needs 12 bits, no base register value

41 ©2009 DJ Foreman Hex Address Purpose (all PSW's: 8 bytes each) 0Initial PSW 8Initial CCW1 10Initial CCW2 18-3FOld PSW's (Ext, SVC, Pgm, Mck, I/O) 58-7FNew PSW's ( '' ) 86-89Interrupt codes (ext, svc, pgm) 2 bytes each BC-BFI/O int parameter (4 bytes) C0-FFReserved st possible byte of O/S or Program

42 ©2009 DJ Foreman Boot Sequence ROM forces an I/O read: –24 bytes from Cyl 0, Hd 0, Rec 0 –Into loc 0, with chaining to loc 8 –These 24 bytes contain PSW 0state vector w/Addr of 1 st byte of pgm CCW1Read more data CCW2And more data CCW Chaining continues at loc 8 At end of data, PSW is loaded Execution begins

43 ©2009 DJ Foreman Program State Management LPSW - Load Program Status Word –Loads address of NSI –Sets privilege mode for NSI –Sets wait state on/off for NSI –Enables/disables interrupts for NSI –Sets memory protection mask for NSI

44 ©2009 DJ Foreman VM Simulation Boot minidisk formatted as a CMS disk –Not a free-standing drive –Temp disk is usable O/S module created in CMS O/S file copied to boot disk Stand-Alone Program Loader (SAPL) installed on boot using SAPIPL When drive is booted, SAPL loads the O/S O/S may then use any volumes (but must either create a file system or use CMS file system

45 ©2009 DJ Foreman Using VM Some CP & CMS commands

46 ©2009 DJ Foreman What is VM? A virtual environment –Minidisks –Virtual devices (some are true simulations) –Spool management (prt, con) –Real-system resource mgr –Privilege-mode emulator for virtual machines –Allows a user to Invoke ALL real hw instructions in a program Boot an O/S - existing or roll-your-own

47 ©2009 DJ Foreman What is VM? - 2 Two components –CP the Control Program or Hypervisor Does all real I/O, paging, scheduling Manages virtual devices (disks, consoles, etc) –CMS the "shell" that comes with VM File system Program management –No multi-threading –No multi-programming Extensive s/w development & file mgmt commands

48 ©2009 DJ Foreman Program creation Xedittext mode editor –Command line for issuing commands HLASMtranslates assembler source –Hlasm myos LOADcollects compiled files –Load myos (RLDSAVE –RLDSAVE keeps relocation dictionary in file for SAPL GENMODlink-edits the LOADed files –Gen myos Scripting language:REXX

49 ©2009 DJ Foreman Booting your own system Define T3390 as vaddr cyl n Format vaddr modeletter Format vaddr modeletter n-1 (recomp Salipl vaddr (origin xxxx mod myos #CP IPL vaddr –Need the #CP to avoid terminal type problems Returning to the CMS shell –#CP IPL CMS Modeletter: –A-Z, same as a PC –Defines path for files AND writeability of drive


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