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ARM 2007 Chapter 13 Memory Protection Unit (MPU) Optimization Technique in Embedded System (ARM) 2008 April.

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Presentation on theme: "ARM 2007 Chapter 13 Memory Protection Unit (MPU) Optimization Technique in Embedded System (ARM) 2008 April."— Presentation transcript:

1 ARM 2007 Chapter 13 Memory Protection Unit (MPU) Optimization Technique in Embedded System (ARM), 2008 April

2 ARM 2007 Overview MPU –Overlapping regions –Background regions Initialize MPU, Cache, Write-Buffer Case: MPU

3 ARM 2007 Memory Protection In a protected system (ARM MPU) –There are two major classes of resources that need monitoring: »Memory, I/O (maybe memory-mapping) –Uses regions to manage system regions. A “region” is a set of attributes (stored in CP15 registers) associated with an area of memory: »Area Scope = {start_addr, len}, 2^N (4KB~4GB) »Access rights –.

4 ARM 2007 Memory Access Sequence When ARM core generates an address, –MPU will check if it falls into any region »If NOT, the memory access is aborted; »If YES, the C, B and AP bits associated with this region are read out. C: Cacheable B: Buffered AP: Access Permission While MPU is disabled –All memory access are treated as uncachable, unbufferable, and non-aborting.

5 ARM 2007 13.1 Protected Regions There are 7 rules that govern regions –Overlay Regions »regions can overlap each other. –Priority Region »Region is assigned a priority number that is independent of privilege assigned to the region. –Attributes Conflict »When regions overlay, attributes of the region with higher priority take precedence over the other regions. –Starting address »Region’s start address = N x Size –Size = 2^N (4KB ~ 4GB); –Exception »Accessing an area of main memory outside a defined region results in an “abort” exception (Prefetch or Data Abort).

6 ARM 2007 13.1.1 Overlapping Regions Overlapping regions –The protection unit can be programmed with two or more overlapping regions. –When overlapping regions are programmed, a fixed priority scheme is applied to determine the region whose attributes are applied to memory access. Overlapping vs. Nonoverlapping –More flexibility

7 ARM 2007 region 0 region 3 13.1.2 Background Regions Another useful feature provided by overlapping regions is background region –Background region with low-priority region used to assign the same attributes to a larger memory area. –Other regions with higher priority are then placed over this background region to change the attributes of a smaller subset of the defined background region. For example –task1 cannot access the regions outside it. task3 task2 task1 (lower priority)

8 ARM 2007 13.2 Initializing the MPU The following steps are required to initialize the MPU, Cache and Write-buffer –Define the regions »In order to initialize the MPU, cache, and write buffer, the control system must define the protection regions required during the target operation. »At a minimum the control system must define at least one data region and one instruction region before or at the same time as the caches and write buffer are enabled. –Set attributes “AP, Cache and Write Buffer “ of each region. –Enable MPU and cache/write buffer.

9 ARM 2007 MPU & CP15 registers Initialization with CP15 registers –Define the size and location of instruction and data regions using CP15:c6; –Set the access permission for each region using CP15:c5; –Set the cache and WB attributes for each region using CP15:c2 for cache and CP15:c3 for the write buffer; –Enable the caches and the MPU using CP15:c1.

10 ARM 2007 13.2.1 Define Region Size and Location Set up 8 regions’ size and location –via CP15:c6:c0:0/1 ~ CP15:c6:c7:0/1 (note: Location should be the multiple of its size) »Size = 2^(N+1) »E: 1=enable, 0=disable For example: Set up Region 3 –start_addr = 0x300000, size =256KB, DATA –Code »MOV r1, #0x300000; »ORR r1, r1, #0x11<<1; size = 256KB »MCR p15, 0, r1, c6, c3, 0

11 ARM 2007 13.2.2 Access Permission Four primary Access Permissions (APs) – MCRp15, 0, Rx, c5, c0, [0|1|2|3] »0 = standard Data Region AP »1= standard Data Region AP »2/3 = extended Data/Instr. AP SupervisorUserAP Code N/A 00 R/WN/A01 R/WRO10 R/W 11

12 ARM 2007 Why not the op2?

13 ARM 2007 13.2.3 Set Region’s cache & WB Three Control Registers in CP15 –CP15:c2:c0:0 —— all data regions Cache enable bits –CP15:c2:c0:1 —— all instruction regions Cache –CP15:c3:c0:0 —— Write Buffer applied data regions

14 ARM 2007 Region Attributes Control region’s Cache and Write-buffer Instr. Cache Data Cache Instr. need no WB

15 ARM 2007 13.2.4 Enable Region & MPU Last 2 steps –Enable regions; –via CP15:c6:c0:0~CP15:c6:c7:0 –Enable MPU hardware (MPU, Cache, WB); »via CP15:c1:c0:0 I (I-Cache): 0=disable, 1=enable C (D-Cache): 0=disable, 1=enable M (MPU): 0=disable, 1=enable SBZ[31:13] 987654101132C2C 10M0M 12 I Start_addr[31:12]SBZ[11:6]N[5:1]E

16 ARM 2007 Summary Region based MPU –A region is a memory set with specific attribution; –Regions can be overlapped (with priority); Initialize MPU units (steps) –1) Set up Start_addr & Size (CP15:c6); –2) Set up APs (CP15:c5); –3) Set attribute of regions: »cache (CP15:c2), write buffer (CP15:c3) –4-a) Enable regions (CP15:c6, again) –4-b) Enable cache, WB and MPU (CP15:c1)

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