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**Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu**

Engineering 43 Diodes-2 Bruce Mayer, PE Registered Electrical & Mechanical Engineer

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Learning Goals Understand the Basic Physics of Semiconductor PN Junctions which form most Diode Devices Sketch the IV Characteristics of Typical PN Junction Diodes Use the Graphical LOAD-LINE method to determine the “Operating Point” of Nonlinear (includes Diodes) Circuits

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**Learning Goals Analyze diode-containing Voltage-Regulation Circuits**

Use various math models for Diode operation to solve for Diode-containing Circuit Voltages and/or Currents Learn The difference between LARGE-signal and SMALL-Signal Circuit Models IDEAL and PieceWise-Linear Models

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Diode Models LoadLine Analysis works well when the ckt connected to a SINGLE Diode can be “Thevenized” However, for NONLinear ckts, such as those containing multiple diodes, construction of the LOAD-Curve Eqn may be difficult, or even impossible. Many such ckts can be analyzed by Idealizing the diode

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**Diode Models Consider an Electrical Diode →**

V I Consider an Electrical Diode → We can MODEL the V-I Behavior of this Device in Several ways IDEAL Model REAL Behavior OFFSET Model LINEAR Model Mr. Phillips described the linear model as the KNEE Voltage-Offset plus Rb = delV/delI

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**Ideal Model (Ideal Rectifier)**

Diode ON Diode OFF Analyze Ckts containing Ideal Diodes Assume (or Guess) a “state” for each diode. Ideal Diodes have Two states ON → a SHORT Ckt when Fwd Biased OFF →an OPEN Ckt if Reverse Biased Check the Assumed Opens & Shorts Should have Current thru the SHORTS Should have ∆V across the OPENS

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**Ideal Model (Ideal Rectifier)**

Diode ON Diode OFF Check to see if guesses for i-flow, ∆V, and BIAS-State are consistent with the Ideal-Diode Model If i-flow, ∆V, and bias-V are consistent with the ideal model, then We’re DONE. If we arrive at even a SINGLE Inconsistency, then START OVER at step-1

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**Example Ideal Diode Find For Ckt Below find:**

Use the Ideal Diode Model

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**Example Ideal Diode In this Case VD1 = VD2 = 0**

Thus D2 Anode is connected to GND Then Find by Ohm Next use KCL at Node-A (in = out) D2 anode connected to GND thru D1, which as VD1 = 0, since it also conducts. This makes a “short” between GND and pt-A. The current on thru RHS of the KCL eqn is the current thru R1 Assume BOTH Diodes are ON or Conducting

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**Example Ideal Diode Thus**

Now must Check that both Diodes are indeed conducting From the analysis Thus the current thru both Diodes is positive which is consistent with the assumption Using ID2 = 1 mA

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Example Ideal Diode Another way to think about this is that since VD2 = 0 and VD1 = 0 (by Short Assumption) Find Vo = GND+VD2+VD1 = GND = 0 Thus the Answer Since both Diodes conduct the Top of Vo is connected to GND thru D2 & D1

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**Example Ideal Diode Find For Ckt Below find:**

Use the Ideal Diode Model Note the different values on R1 & R2 Swapped

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**Example Ideal Diode As Before VD1 = VD2 = 0**

Again VB shorted to GND thru D1 Then Find by Ohm Now use KCL at Node-B (in = out) D2 cathode connected to GND thru D1, which as VD1 = 0, since it also conducts Again Assume BOTH Diodes are ON, or Conducting

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**Example Ideal Diode Thus**

Now must Check that both Diodes are indeed conducting From the analysis We find and INCONSISTENCY and our Assumption is WRONG Using ID2 = 1.01 mA

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**Example Ideal Diode In this Case D1 is an OPEN → ID1 =0**

Current ID2 must flow thru BOTH Resistors Then Find by Ohm Must Iterate Assume D1 → OFF D2 → ON

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**Example Ideal Diode By KVL & Ohm**

Thus D1 is INDEED Reverse-Biased, Thus the Ckt operation is Consistent with our Assumption Must Check that D1 is REVERSE Biased as it is assumed OFF

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Example Ideal Diode D2 is ON → VD2 = 0 D1 is OFF → Current can only flow thru D2 In this case Vo = VB By the Previous Calculation, Find Calculate Vo by noting that:

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**Offset & Linear Models The Offset Model**

Better than Ideal, but no account of Forward-Slope The Linear Model The model eqn: Yet more accurate, but also does not account for Rev-Bias Brk-Down Rb depends on the physical SIZE of the diode; specifically the Cross-Section of the PN jcn. Neither Model accounts for Rev-Bias BreakDown => Need to Add Another Line-Segment to these piecewise Linear Models.

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Point Slope Line Eqn When constructing multipiece-wise linear models, the Point-Slope Equation is extremely Useful Where (x1, y1) & (x2, y2) are KNOWN Points Example: Find Eqn for line-segment: (3,17) (19,5) MATLAB Session in Command Window → x =[3, 19]; y = [17,5]; plot(x,y, 'd', x,y, 'LineWidth',3), grid, xlabel('x'), ylabel('y')

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**Point Slope Line Eqn Using the 2nd Point**

Can easily convert to y = mx+b Multiply by m, move −5 to other side of = (3,17) (19,5)

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Slopes on vi Curve With Reference to the Point-Slope eqn v takes over for x, and i takes over for y The Slope on a vi Curve is a conductance If the curve is NONlinear then the local conductance is the first Derivative Recall the Op-Pt is also the Q-Pt Mr. Phillips talked about the small-signal transconductance in the MOSFET Lab

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Slopes on vi Curve Finally recall that conductance & resistance are Inverses Example: Find the RESISTANCE of the device associated with the VI curve that follows V =[3, 19]; I = [17,5]; plot(x,y, 'd', x,y, 'LineWidth',3), grid, xlabel('V'), ylabel('I'), title('Linear VI Curve')

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**Slopes on vi Curve Since R = 1/G Find the Device Resistance as**

For a NONlinear vi curve the local slope then: r = 1/g The General Reln

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**Example PieceWise Linear Model**

Construct a PieceWise Linear Model for the Zener vi curve shown at Right

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**PieceWise Linear Zener**

Us Pt-Slp eqn with (0.6V,0mA) for Pt-1 Segment- B is easy m for Segment A

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**PieceWise Linear Zener**

Us Pt-Slp eqn with (−6V,0mA) for Pt-1 Thus the PieceWise Model for the Zener m for Segment C

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**Example PieceWise Linear Model**

Alternatively in terms of Resistances ADVICE: remember the Pt-Slope Line-Eqn

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**Half-Wave Rectifier Ckt**

Consider an Sinusoidal V-Source, such as an AC socket in your house, supplying power to a Load thru a Diode 0.7 is the OffSet, or Knee voltage Power Input Load Voltage

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HalfWave Rectifier Note that the Doide is FWD-Biased during only the POSITIVE half-cycle of the Source Using this simple ckt provides to the load ONLY positive-V; a good thing sometimes However, the positive voltage comes in nasty PULSES which are not well tolerated by positive-V needing loads

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**Smoothed HalfWave Rectifier**

Adding a Cap to the Circuit creates a Smoothing effect In this case the Diode Conducts ONLY when vs>vC and vC=vL This produces vL(t) and iL(t) curves Note that iL(t) is approx. constant Recall the Caps Resist Voltage-Changes across them. Vr is the RIPPLE Voltage

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**Smoothed HalfWave Rectifier**

The change in Voltage across the Cap is called “Ripple” Often times the load has a Ripple “Limit” from which we determine Cap size From the iL(t) curve on the previous slide note: Cap Discharges for Almost the ENTIRE Cycle time, T (diode Off) The Load Current is approx. constant, IL Recall from EARLY in the Class Ripple

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**Smoothed HalfWave Rectifier**

Also from Cap Physics (chp3) In the Smoother Ckt the Cap charges during the “Ripple” portion of the curve Equating the Charge & Discharge “Q’s find Note that both these equations are Approximate, but they are still useful for initial Ckt Design Solving the equations for the Cap Value needed for a given Vr Charge Discharge

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**Smoothed HalfWave Rectifier**

Find the Approximate Average Load Voltage VL,hi VL,lo

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**Capacitor-Size Effect**

Any load will discharge the capacitor. In this case, the output will depend on how the RC time constant compares with the period of the input signal. The plots at right consider the various cases for the simple circuit above with a 1kHz, 5V sinusoidal input

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Full Wave Rectifier The half-wave ckt will take an AC-Voltage and convert it to DC, but the rectified signal has gaps in it. The gaps can be eliminated thru the use of a Full-Wave rectifier ckt The Diodes are Face-to-Face (right) Butt-to-Butt (left) This rectified output has NO Gaps

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**Full Wave Rectifier Operation**

D1 Supplies V to Load Explain that transformer merely reduces the amplitude of the sinusoidal signal. The current makes its way back to the source thru the GND connections D4 Supplies V to Load

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**Full Wave Rectifier Smoothing**

The Ripple on the FULL wave Ckt is about 50% of that for the half-wave ckt Since the Cap DIScharges only a half-period compared to the half-wave ckt, the size of the “smoothing” cap is then also halved:

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Small Signal Models Often we use NonLinear Circuits to Amplify, or otherwise modify, non-steady Signals such as ac-sinusoids that are small compared to the DC Operating Point, or Q-Point of the Circuit. Over a small v or i range even NonLinear devices appear linear. This allows us to construct a so-called small signal Linear Model

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Small Signal Analysis Small signal Analysis is usually done in Two Parts: Large-Signal DC Operating Point (Q-Pt) Linearize about the Q-Pt using calculus Recall from Calculus This approximation become more accrate as ∆y & ∆x become smaller

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**Small Signal Analsyis Now let y→iD, and x→ vD**

Use a DC power Supply to set the operating point on the diode curve as shown at right This could be done using LoadLine methods From Calculus Next Take derivative about the Q-Pt

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**Small Signal Analysis About Q-Pt**

Now if we have a math model for the vi curve, and we inject ON TOP of VDQ a small signal, ∆vD find The derivative is the diode small-signal Conductance at Q

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**Small Signal Analysis In the large signal Case: R = 1/G**

By analogy In the small signal case: r = 1/g Also since small signal analysis is associated with small amounts that change with time… Define the Diode’s DYNAMIC, small-signal Conductance and Resistance

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**Small Signal Analysis Note Units for rd**

Recall the approximation for iD Change Notation for Small Signal conditions Find rd for a “Shockley” Diode in majority FWD-Bias Recall Shockley Eqn Then the Large-signal Operating Point at vD = VDQ The last approximation is for significant FWD bias → VDQ >> nVT

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**Small Signal Analysis Taking the derivative of the Shockely Eqn**

Recall from last sld Sub this Reln into the Derivative Eqn Recall Subbing for diD/dvD The last approximation is for significant FWD bias → VDQ >> nVT

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**Notation: Large, Small, Total**

VDQ and IDQ are the LARGE Signal operating point (Q-Pt) DC quantities These are STEADY-STATE values vD and iD are the TOTAL and INSTANTANEQOUS quantities These values are not necessarily steady-state. To emphasize this we can write vD(t) and iD(t)

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**Notation: Large, Small, Total**

vd and id are the SMALL, AC quantities These values are not necessarily steady-state. To emphasize this we can write vd(t) and id(t) An Example for Diode Current notation

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**Effect of Q-Pt Location**

From Analysis Same id, but different vd’s result from the location of the Q-point and rd calculation

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**DC Srcs SHORTS in Small-Signal**

In the small-signal equivalent circuit DC voltage-sources are represented by SHORT CIRUITS; since their voltage is CONSTANT, they exhibit ZERO INCREMENTAL, or SIGNAL, voltage Alternative Statement: Since a DC Voltage source has an ac component of current, but NO ac VOLTAGE, the DC Voltage Source is equivalent to a SHORT circuit for ac signals

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**Setting Q, Injecting v Consider this ckt with AC & DC V-srcs Sets Q**

Note the coupling capacitor: Zc = i/(jwC) Sets vd

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**Large and Small Signal Ckts**

Recall from Chps 3 and 5 for Caps: OPENS to DC SHORTS to fast AC Thus if C1 is LARGE it COUPLES vin(t) with the rest of the ckt Similarly, Large C2 couples to the Load To Find the Q-point DEcouple vin and vo to arrive at the DC circuit

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**Large and Small Signal Ckts**

Finding the Large signal Model was easy; the Caps acts as an OPENS The Small Signal Ckt needs more work Any DC V-Supply is a SHORT to GND The Diode is replaced by rd (or gd) The Caps are Shorts Thus the Small Signal ckt for the above

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**Example: Small Signal Gain**

Find the Small Signal Amplification (Gain), Av, of the previous circuit Using the Small Signal Circuit Note that RC, rd, and RL are in Parallel And vo(t) appears across this parallel combination The equivalent ckt

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**Example: Small Signal Gain**

Thus for this Ckt the Large, Small, and small-Equivalent ckts Then the Amplification (Gain) by Voltage Divider

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**Small Signal BJT Amp All Done for Today Common Collector Amplifier**

LARGE Signal Model All Done for Today Small Signal BJT Amp Nobel Prize in Physics (1956). Difficult man to work for whom to work – Pain in Butt… Common Collector Amplifier SMALL Signal Model

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**Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu**

Engineering 43 Appendix Bruce Mayer, PE Registered Electrical & Mechanical Engineer

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**Small Signal Analysis In the large signal Case: R = 1/G**

By analogy In the small signal case: r = 1/g Also since small signal analysis is associated with small amounts that change with time… Define the Diode’s DYNAMIC Conductance and Resistance

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P10.67 Graph vo vs. vi for vi: −5V to +5V

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