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Notation SOP and POS Forms. SOP Given a Table of Combinations  What is the SOP form for the following 3 input / 1 output digital device? SABf 0000 0010.

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Presentation on theme: "Notation SOP and POS Forms. SOP Given a Table of Combinations  What is the SOP form for the following 3 input / 1 output digital device? SABf 0000 0010."— Presentation transcript:

1 Notation SOP and POS Forms

2 SOP Given a Table of Combinations  What is the SOP form for the following 3 input / 1 output digital device? SABf

3 Computing the SOP (2)  This SOP has 4 minterms: f = S'AB' + S'AB + SA'B + SAB SABfminterm name 0101m2m2 0111m3m3 1011m5m5 1111m7m7

4 Canonical SOP  Boolean functions can use shorthand notation when in SOP form: f = S'AB' + S'AB + SA'B + SAB f(S,A,B) =  (m 2,m 3,m 5,m 7 ) or f(S,A,B) =  m(2,3,5,7)

5 Canonical SOP Example  f(x 1,x 2,x 3 ) =  m(1,4,5,6)  f = mintermx1x1 x2x2 x3x3 f x1'x2'x3 + x1x2'x3' + x1x2'x3 + x1x2x3'

6 Product of Sums Form  An alternate canonical “two-level” format “Product of sums”  POS Two levels  OR level followed by AND level  Again, NOT doesn’t count as a level Not a common as SOP, but can be useful in some situations  Which ones?

7 Computing the POS  Identify rows with “0” on output (f = 0)  Represent the input for each 0 row as a maxterm A logical “sum” of the input bits which guarantees that term will be “0” (sum of literals) ABf

8 Canonical POS Example  f(x 1,x 2,x 3 ) =  ( M 0,M 2,M 3,M 7 ) =  M(0,2,3,7)  f = maxtermx1x1 x2x2 x3x3 f (x1+x2+x3)(x1+x2'+x3)(x1+x2'+x3')(x1'+x2'+x3')

9 Example: 3 Way Light Control  L(A,B,C) =  m(5,6) or L(A,B,C) =  M(0,1,2,3,4,7)  SOP: L =  POS: L = ABCL (A B' C)+(A B C') (A+B+C)(A+B+C') (A+B'+C)(A+B'+C') (A'+B+C)(A'+B'+C')

10 Question:  Under what conditions would POS form be better? (assuming we aren’t doing further reductions)

11 Inverters in Two-Level Circuits  Inverters are not always required for two-level logic This is why we do not always count them among the cost of a circuit  Later, we will see that many variables will be available to us in both normal and inverted form  don't need to invert them  We show them only for completeness at this point

12 NAND/NOR Circuits

13 Completeness of NAND Any Boolean function can be implemented using just NAND gates. Why?  Need AND, OR, and NOT  NOT: 1-input NAND (or 2-input NAND with inputs tied together)  AND: NAND followed by NOT  OR: NAND preceded by NOTs Likewise for NOR

14 Using NAND as Universal Logic  NOT  AND  OR

15 SOP Using NORs & POS Using NANDs  NANDs are natural for SOP networks You can extend this idea to multi-level circuits as long as the levels alternate AND/OR/AND/OR ending with OR You can implement an SOP circuit using only NOR gates  All gates become NORs; just add an extra “inverter” following the final NOR  NORs are natural for POS networks You can extend this idea to multi-level circuits as long as the levels alternate OR/AND/OR/AND ending with AND You can implement a POS circuit using only NAND gates  All gates become NANDs; just add an extra inverter following the final NAND

16 SOP Using NAND Networks  SOP can be implemented with just NAND gates “pushing the bubbles” Every gate just becomes a NAND!

17 2x1 MUX Using NANDs  Implement f = S'A + SB with NAND gates only  This one is complicated by the inverter on S!

18 POS Using NOR Networks  POS can be implemented with just NOR gates Every gate just becomes a NOR

19 Schematics of DeMorgan’s Laws (x ∙ y)' = x' + y' (x + y)' = x' ∙ y'

20 Universal Logic Families  Any logic function can be designed using only: AND, OR, NOT NAND NOR  These are called “universal logic families”  Actual components are often designed using either NAND or NOR gates only NAND and NOR require fewer transistors to build Just having a single gate design is simpler than having 3!

21 AND/OR Networks  NAND/NAND  Convert multi-level AND/OR net  NAND/NAND

22 And Again … But Be Careful conserve the polarity of the input/output signals

23 Some Useful Circuits

24 Decoders and Multiplexors Decoder: Popular combinational logic building block, in addition to logic gates  Converts input binary number to one high output 2-input decoder: four possible input binary numbers  So has four outputs, one for each possible input binary number Internal design  AND gate for each output to detect input combination Decoder with enable e  Outputs all 0 if e=0  Regular behavior if e=1 n-input decoder: 2 n outputs i0 i1 d0 d1 d2 d i0 i1 d0 d1 d2 d i0 i1 d0 d1 d2 d3 i0 i1 d0 d1 d2 d i0 d0 d1 d2 d3 i1 i0 i1 d0 d1 d2 d3 e e i0 i1 d0 d1 d2 d i1’i0’ i1’i0 i1i0’ i1i0

25 Multiplexor (Mux) Mux: Another popular combinational building block  Routes one of its N data inputs to its one output, based on binary value of select inputs 4 input mux  needs 2 select inputs to indicate which input to route through 8 input mux  3 select inputs N inputs  log 2 (N) selects  Like a railyard switch

26 Mux Internal Design s0 d i0 i1 2 × 1 i0 s0 1 d 2 × 1 i1 i0 s0 0 d 2 × 1 i1 i0 s0 d 0 i0 (1*i0=i0) i0 (0+i0=i0) 1 0 2x1 mux i0 4  1 i2 i1 i3 s1s0 d d i0 i1 i2 i3 s1 4x1 mux 0 a

27 Muxes Commonly Together -- N-bit Mux Ex: Two 4-bit inputs:  A (a3 a2 a1 a0) and B (b3 b2 b1 b0)  4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B i0 s0 i1 2  1 d i0 s0 i1 2  1 d i0 s0 i1 2  1 d i0 s0 i1 2  1 d a3 b3 I0 s0 I1 4-bit 2x1 DC A B a2 b2 a1 b1 a0 b0 s0 4 C c3 c2 c1 c0 is short for Simplifying notation:

28 N-bit Mux Example Four possible display items  Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide  Choose which to display using two inputs x and y  Use 8-bit 4x1 mux


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