# CENG 241 Digital Design 1 Lecture 6 Amirali Baniasadi

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CENG 241 Digital Design 1 Lecture 6 Amirali Baniasadi amirali@ece.uvic.ca

2 Decimal adder zWhen dealing with decimal numbers BCD code is used. zA decimal adders requires at least 9 inputs and 5 outputs. zBCD adder: each input does not exceed 9, the output can not exceed 19 zHow are decimal numbers presented in BCD? zDecimal Binary BCD z 9 1001 1001 z19 10011 (0001)(1001) z 1 9

3 Decimal Adder zDecimal numbers should be represented in binary code number. zExample: BCD adder zSuppose we apply two BCD numbers to a binary adder then: zThe result will be in binary and ranges from 0 through 19. zBinary sum: K(carry) Z8 Z4 Z2 Z1 zBCD sum : C(carry) S8 S4 S2 S1 zFor numbers equal or less than 1001 binary and BCD are identical. zFor numbers more than 1001, we should add 6(0110) to binary to get BCD. zexample: 10011(binary) = 11001(BCD) =19 zADD 6 to correct.

4 BCD adder Decides to add 6? Adds 6 Numbers that need correction (add 6) are: 01010 (10) 01011 (11) 01100 (12) 01101 (13) 01110 (14) 01111 (15) 10000 (16) 10001 (17) 10010 (18) 10011 (19)

5 BCD adder Numbers that need correction (add 6) are: K Z8 Z4 Z2 Z1 0 1 0 1 0 (10) 0 1 0 1 1 (11) 0 1 1 0 0 (12) 0 1 1 0 1 (13) 0 1 1 1 0 (14) 0 1 1 1 1 (15) 1 0 0 0 0 (16) 1 0 0 0 1 (17) 1 0 0 1 0 (18) 1 0 0 1 1 (19) C = K + Z8Z4 +Z8Z2

6 Magnitude Comparators zCompares two numbers, determines their relative magnitude. zWe look at a 4-bit magnitude comparator; zA=A3A2A1A0, B=B3B2B1B0 zTwo numbers are equal if all bits are equal. zA=B if A3=B3 AND A2=B2 AND A1=B1 AND A0=B0 zXi= AiBi + Ai’Bi’ ; Ai=Bi Xi=1 (remember exclusive NOR?)

7 Magnitude Comparators zHow do we know if A>B? z1.Compare bits starting from the most significant pair of digits z2.If the two are equal, compare the next lower significant bits z3.Continue until a pair of unequal digits are reached z4.Once the unequal digits are reached, A>B if Ai=1 and Bi=0, AB = A3B3’+X3A2B2’+X3X2A1B1’+X3X2X1A0B0’ zA { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/11/3311934/slides/slide_7.jpg", "name": "7 Magnitude Comparators zHow do we know if A>B.", "description": "z1.Compare bits starting from the most significant pair of digits z2.If the two are equal, compare the next lower significant bits z3.Continue until a pair of unequal digits are reached z4.Once the unequal digits are reached, A>B if Ai=1 and Bi=0, AB = A3B3’+X3A2B2’+X3X2A1B1’+X3X2X1A0B0’ zA

8 Magnitude Comparators A3=B3 ? X3A2’B2

9 Decoders zA decoder converts binary information from n input lines to a maximum of 2 n output lines zAlso known as n-to-m line decoders where m< 2 n zExample 3-to-8 decoders.

10 Decoders: Truth Table zX Y Z D0 D1 D2 D3 D4 D5 D6 D7 z0 0 0 1 0 0 0 0 0 0 0 z0 0 1 0 1 0 0 0 0 0 0 z0 1 0 0 0 1 0 0 0 0 0 z0 1 1 0 0 0 1 0 0 0 0 z1 0 0 0 0 0 0 1 0 0 0 z1 0 1 0 0 0 0 0 1 0 0 z1 1 0 0 0 0 0 0 0 1 0 z1 1 1 0 0 0 0 0 0 0 1

11 Decoders: AND implementation

12 2-to-4 Decoder: NAND implementation Decoder is enabled when E=0

13 How to build bigger decoders? We can combine two 3-to-8 decoders to build a 4-to-16 decoder. Generates from 0000 to 0111 Generates from 1000 to 1111

14 zA decoder provides the 2n minterms of n input variables. zAny function is can be expressed in sum of minterms. zUse a decoder to make the minterms and an external OR gate to make the sum. zExample: consider a full adder. zS(x,y,z) = Σ(1,2,4,7) zC(x,y,z) = Σ (3,5,6,7) Combinational Logic implementation

15 Combinational Logic implementation

16 Encoders zEncoders perform the inverse operation of a decoder: zEncoders have 2 n input lines and n output line. zOutput lines generate the binary code corresponding to the input value.

17 Encoders: Truth Table z Outputs Inputs zX Y Z D0 D1 D2 D3 D4 D5 D6 D7 z0 0 0 1 0 0 0 0 0 0 0 z0 0 1 0 1 0 0 0 0 0 0 z0 1 0 0 0 1 0 0 0 0 0 z0 1 1 0 0 0 1 0 0 0 0 z1 0 0 0 0 0 0 1 0 0 0 z1 0 1 0 0 0 0 0 1 0 0 z1 1 0 0 0 0 0 0 0 1 0 z1 1 1 0 0 0 0 0 0 0 1 zz=D1+D3+D5+D7 y=D2+D3+D6+D7 x=D4+D5+D6+D7

18 Priority Encoders zEncoder limitations: zIf two inputs are active, the output is undefined. zSolution: we need to take into account priority. zWhat if all inputs are 0? zSolution: we need a valid bit z Input Output zD0 D1 D2 D3 x y v z0 0 0 0 X X 0 z1 0 0 0 0 0 1 zX 1 0 0 0 1 1 zX X 1 0 1 0 1 zX X X 1 1 1 1

19 Priority Encoders: Map

20 Priority Encoders: Circuit

21 Multiplexers zMultiplexer: selects one binary input from many selections zexample: 2-to-1 MUX

22 4-to-1 MUX Directs 1 of the 4 inputs to the output

23 Multi-bit selection logic zMultiplexers can be combined with common selection inputs to support multi-bit selection logic

24 Implementing Boolean functions w/ MUX zGeneral rules for implementing any Boolean function with n variables: zUse a multiplexer with n-1 selection inputs and 2 n-1 data inputs zList the truth tabel zApply the first n-1 variables to the selection inputs of multiplexer zFor each combination evaluate the output as a function of the last variable. zThe function can be 0, 1 the variable or the complement of the variable.

25 Implementing Boolean functions w/ MUX

26 Implementing Boolean functions w/ MUX

27 Summary zReading up to page 154