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00/00/2008 1 Tunnel dielectric Trapping layer Blocking layer Gate material SiO 2 (nitrided) Si 3 N 4 Al 2 O 3 Ta Standard TANOS Options investigated in.

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Presentation on theme: "00/00/2008 1 Tunnel dielectric Trapping layer Blocking layer Gate material SiO 2 (nitrided) Si 3 N 4 Al 2 O 3 Ta Standard TANOS Options investigated in."— Presentation transcript:

1 00/00/ Tunnel dielectric Trapping layer Blocking layer Gate material SiO 2 (nitrided) Si 3 N 4 Al 2 O 3 Ta Standard TANOS Options investigated in GOSSAMER SiO 2 different growth conditions Nitrided SiO 2 different growth conditions BE dielectric (SiO 2 /Si 3 N 4 /HTO or re-ox) Si 3 N 4 different stochiometries HfO 2 different deposition/thermal treatment ZrO 2 different deposition/thermal treatment ZrAlO and ZrSiO nanolaminates LaAlO nanolaminates Al 2 O 3 different deposition/thermal treatment “ “ with SiO 2 buffer layers HfAlO, LaAlO DyScO, GdScO, TbO, TbSCO TiN TaN different deposition TaC technologies TaCN

2 00/00/ Gb TANOS demonstrator Picture of 1Gbit NAND Charge Trap Flash Numonyx inserted the Charge Trap cell into a 1Gbit 1.8V NAND device adapting cell pitch at row and column decoders thanks to an advanced copper metallization The device includes 1.8 billion cells but only 1 G is addressable due to the re-use of an existing cell design. ~40nm 500Mbit array RAM Schematic layout

3 00/00/ nm demonstration 3 – In Self-Aligned structure, W narrowing increases P/E efficiency – Down to 1x nm node we estimate no significant degradation of P/E windows 4Mbit addressable array at 25nm

4 00/00/ D architectures 30nm 25nm OXIDE gate - Effect of floating body channel - Effect of poly-silicon channel - Effect of wrap-around SONOS cell Multi-plane architectureVertical SONOS Cell(imec) Program v.s. diameter programming voltage


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