Presentation on theme: "DIAMOND: Targeting Verification and Reliability Issues in Systems"— Presentation transcript:
1DIAMOND: Targeting Verification and Reliability Issues in Systems Jaan Raik
2DIAMOND: Targeting Verification and Reliability Issues in Systems EU FP7 STREP Project DIAMONDA holistic view of design and soft errorsSuccess stories:FoREnSiC (C, system-level)zamiaCAD (VHDL/Verilog/SC, RTL)Follow-up projectsSignificance to CEBE
4diagnosis/correction The DIAMOND conceptSoft-errors caused by cosmic radiationDesign mistakes made by the engineerDIAMOND’sdiagnosis/correctionmethodsSoft-errors in new generation chips due to background radiationElectronic systems fail while working in the field
5DIAMOND: ObjectivesA unified, holistic diagnostic model for bugs and soft errors at all levels;Automated localisation & correction techniques based on the unified model, both pre-silicon & post-silicon;Implementation of a reasoning framework for localisation & correction, encompassing word-level techniques, formal, semi-formal, and dynamic techniques.
6DIAMOND: FP7 collaborative research FP ICT DIAMOND - Diagnosis, Error Modelling and Correction for Reliable Systems DesignStart January 2010; total budget 3.8M € (EU contribution 2.9M €); PMThe IBM logo is a registered trademark of International Business Machines Corporation (IBM) in the United States and other countries.DIAMOND Kick-off, Tallinn, February 2-3, 2010
7Verification and debug ~2/3 of development time for verification~2/3 of verification time for debugThus, nearly half of the development cycle!Automation of the debug step needed...
8Traditional debug flow ???SpecDesignCounter-examples (waveforms), failed assertions, ...VerificationError!Too little informationToo much information
10DIAMOND Debug Tools FoREnSiC Formal automated debug environment for ESL HW in CzamiaCADA highly scalable framework for design analysis and automated debug at RTL (VHDL-centric)
11FoREnSiC FoREnSiC: Formal Repair Environment for Simple C For system-level HWDeveloped by TU Graz, University of Bremen and TUTFront-end converting simple C descriptions to flowchart model, different debug back-endsOpen source and available at:
13Available FoREnSiC Back-Ends FoREnSiC includes 3 complementary back-ends:Symbolic back-end (TU Graz)Symbolic+concolic engines and model-based diagnosis for localization; template-based correction.Cut-based back-end (University of Bremen)Formally verifies the equivalence between a C program and an implementation in HDL.Simulation-based back-end (Tallinn University of Technology, University of Verona)Intended for correcting larger programs. Statistical localization + mutation-based correction