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Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 1 Introduction.

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Presentation on theme: "Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 1 Introduction."— Presentation transcript:

1 Jan M. Rabaey Low Power Design Essentials ©2008 Chapter 1 Introduction

2 Low Power Design Essentials © Why Worry about Power?  Total Energy of Milky Way Galaxy: J  Minimum switching energy for digital gate (1 mV): J (limited by thermal noise)  Upper bound on number of digital operations:  Operations/year performed by 1 billion 100 MOPS computers:  Energy consumed in 180 years, assuming a doubling of computational requirements every year (Moore’s Law). The Tongue-in-Cheek Answer

3 Low Power Design Essentials © Power the Dominant Design Constraint (1) Cost of large data centers solely determined by power bill … Google Data Center, The Dalles, Oregon Columbia River 8, , ,000 NY Times, June 06  400 Millions of Personal Computers worldwide (Year 2000) - Assumed to consume 0.16 Tera (10 12 ) kWh per year - Equivalent to 26 nuclear power plants  Over 1 Giga kWh per year just for cooling - Including manufacturing electricity [Ref: Bar-Cohen et al., 2000]

4 Low Power Design Essentials © Power the Dominant Design Constraint [Ref: R. Schmidt, ACEED’03]

5 Low Power Design Essentials © Chip Architecture and Power Density [Ref: R. Yung, ESSCIRC’02] Integration of diverse functionality on SoC causes major variations in activity (and hence power density) The past: temperature uniformity Today: steep gradients Temperature variations cause performance degradation – higher temperature means slower clock speed

6 Low Power Design Essentials © Temperature Gradients (and Performance) IBM Power PC 4 temperature map [ Ref: R. Schmidt, ACEED’03] Hot spot: 138 W/cm 2 (3.6 x chip avg flux) Glass ceramic substrate SiC spreader (chip underneath spreader) Copper hat (heat sink on top not shown)

7 Low Power Design Essentials © Power the Dominant Design Constraint (2) Mobile Functionality Limited by Energy Budget [Ref: Y. Nuevo, ISSCC’04 ] Size of mobile sets energy supply Power consumption and Battery Capacity Trends © IEEE 2004

8 Low Power Design Essentials © Mobile Functionality Limited by Energy Budget [Ref: F. Snijders, Ambient Intelligence’05] Energy hierarchy in “ambient intelligent” environment © Springer 2005

9 Low Power Design Essentials © Battery Storage a Limiting Factor  Basic technology has evolved little –store energy using a chemical reaction  Battery capacity increases between 3% and 7 % per year (doubled during the 90’s, relatively flat before that)  Energy density/size, safe handling are limiting factor For extensive information on energy density of various materials, check

10 Low Power Design Essentials © Battery Evolution Accelerated since the 1990’s, but slower than IC power growth.

11 Low Power Design Essentials © Battery Technology Saturating Battery capacity naturally plateaus as systems develop [Courtesy: M. Doyle, Dupont]

12 Low Power Design Essentials © Need Higher Energy Density [Ref: R. Nowak, SECA’01] Fuel cells may increase stored energy more than a order of magnitude Example: Methanol = 5 kWh/kg Anode Electrolyte Cathode + ions Load e Fuel 2H 2  4H + + 4e - Oxidant O 2 + 4H + + 4e -  2H 2 O H O

13 Low Power Design Essentials © Fuel Cells Methanol fuel-cells for portable pc’s and mp3 players [Ref: Toshiba, ] Fuel cell for pc (12 W avg – 24% effiency) Portable mp3 fuel cell (300 mW from 10 ml reservoir)

14 Low Power Design Essentials © Micro-batteries When Size is an Issue Battery printed on wireless sensor node Using micro-electronics or thin-film manufacturing techniques to create integrate miniature (back-up) batteries on chip or on board Stencil press for printing patterns [Courtesy: P. Wright, D. Steingart, UCB]

15 Low Power Design Essentials © How much Energy Storage in 1 cm 3 ? J/cm 3  W/cm 3 /year Micro Fuel cell Primary battery Secondary battery Ultracapacitor ultracapacitor Micro fuel cell ultracapacitor

16 Low Power Design Essentials © Power The Dominant Design Constraint (3) Exciting emerging applications require “zero-power ” Example: Computation/Communication Nodes for Wireless Sensor Networks Meso-scale low-cost wireless transceivers for ubiquitous wireless data acquisition that are fully integrated – Size smaller than 1 cm 3 are dirt cheap – At or below 1$ minimize power/energy dissipation – Limiting power dissipation to 100  W enables energy scavenging and form self-configuring, robust, ad-hoc networks containing 100’s to 1000’s of nodes Meso-scale low-cost wireless transceivers for ubiquitous wireless data acquisition that are fully integrated – Size smaller than 1 cm 3 are dirt cheap – At or below 1$ minimize power/energy dissipation – Limiting power dissipation to 100  W enables energy scavenging and form self-configuring, robust, ad-hoc networks containing 100’s to 1000’s of nodes [Ref: J. Rabaey, ISSCC’01]

17 Low Power Design Essentials © How to Make Electronics Truly Disappear? From 10’s of cm 3 and 10’s to 100’s of mW To 10’s of mm 3 and 10’s of  W

18 Low Power Design Essentials © Power the Dominant Design Constraint Exciting emerging applications require “zero-power” Real-time Health Monitoring Smart Surfaces Artificial Skin Philips Sand module UCB mm 3 radio UCB PicoCube Still at least one order of magnitude away

19 Low Power Design Essentials © How much Energy Can One Scavenge in 1 cm 3 ? Thermal Air Flow Solar Vibrations

20 Low Power Design Essentials © A Side Note: What can one do with 1 cm 3 ? Reference case: the human brain P avg (brain) = 20 W (20% of the total dissipation, 2% of the weight), Power density: ~15 mW/cm 3 Nerve cells only 4% of brain volume Average neuron density: 70 million/cm 3

21 Low Power Design Essentials © Power versus Energy  Power in high performance systems –Heat removal –Peak power - power delivery  Energy in portable systems –Battery life  Energy/power in “zero-power systems” –Energy-scavenging and storage capabilites  Dynamic (energy) vs. static (power) consumption –Determined by operation modes

22 Low Power Design Essentials © Power Evolution over Technology Generations Introduction of CMOS over bipolar bought industry 10 years (example: IBM mainframe processors) [Ref: R. Chu, JEP’04] © ASME 2004

23 Low Power Design Essentials © Power Trends for Processors [Ref: T. Sakurai, ISSCC’03] Power per chip [W] Year MPU x4 / 3 years DSP x1.4 / 3 years © IEEE 2003

24 Low Power Design Essentials © Power Density Trend for Processors P = P DYNAMIC (+ P LEAK ) [Ref: T. Sakurai, ISSCC’03] Scaling the Prime Reason! Power density : p [W/cm 2 ] Constant V scaling and long-channel devices  P DYNAMIC  k 3 Constant V scaling and long-channel devices  P DYNAMIC  k 3 Proportional V scaling and short-channel devices  P DYNAMIC  k 0.7 Proportional V scaling and short-channel devices  P DYNAMIC  k 0.7 © IEEE 2003

25 Low Power Design Essentials © Evolution of Supply Voltages in the Past Minimum Feature Size (micron) Supply Voltage (V) Supply voltage scaling only from the 1990’s

26 Low Power Design Essentials © Subthreshold Leakage As an Extra Complication Year 2002’04’06’08’10’12’14’ Technology node[nm] Voltage [V] V TH V DD Technology node 2002’04’06’08’10’12’14’ Year P DYNAMIC P LEAK Power [µW / gate] Subthreshold leak (Active leakage) [Ref: T. Sakurai, ISSCC’03] © IEEE 2003

27 Low Power Design Essentials © Static Power (Leakage) may Ruin Moore ’ s Law Power per chip [W] Year MPU x4 / 3 years DSP x1.4 / 3 years Processors published in ISSCC x1.1 / 3 years ITRS requirement Dynamic Leakage 1/100 [Ref: T. Sakurai, ISSCC 03] © IEEE 2003

28 Low Power Design Essentials © Power Density Increases [Courtesy: S. Borkar, Intel] Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Upper Bound? Unsustainable in the long term

29 Low Power Design Essentials © Projecting Into the Future 2003 ITRS – Low operating power scenario Active power density: k 1.9 Leakage power density: k 2.7 Compute density: k ITRS – Low operating power scenario FD-SOI Dual Gate Power density (active and static) accelerating anew. Technology innovations help, but impact limited.

30 Low Power Design Essentials © Complicating the Issue: The Diversity of SoCs [Ref: many combined sources] Power budgets of leading general purpose (MPU) and special purpose (ASSP) processors

31 Low Power Design Essentials © Supply and Threshold Voltage Trends VDD VT [Ref: ITRS 05, Low power scenario] VDD/VTH = 2! Voltage reduction projected to saturate Optimistic scenario – some claims exist that V DD may get stuck around 1V Slide 1.30

32 Low Power Design Essentials © A 20 nm Scenario [ Ref: S. Borkar, Intel] Assume V DD = 1.2V  FO4 delay < 5 ps  Assuming no architectural changes, digital circuits could be run at 30 GHz  Leading to power density of 20 kW/cm 2 (??) Assume V DD = 1.2V  FO4 delay < 5 ps  Assuming no architectural changes, digital circuits could be run at 30 GHz  Leading to power density of 20 kW/cm 2 (??) Reduce V DD to 0.6V  FO4 delay ≈ 10 ps  The clock frequency is lowered to 10 GHz  Power density reduces to 5 kW/cm 2 (still way too high) Reduce V DD to 0.6V  FO4 delay ≈ 10 ps  The clock frequency is lowered to 10 GHz  Power density reduces to 5 kW/cm 2 (still way too high)

33 Low Power Design Essentials © A 20 nm Scenario (cntd) Assume optimistically that we can design FETs (Dual- Gate, FinFet, or whatever) that operate at 1 kW/cm 2 for FO4 = 10 ps and V DD = 0.6 V [Frank, Proc. IEEE, 3/01]  For a 2cm x 2cm high-performance microprocessor die, this means 4kW power dissipation.  If die power has to be limited to 200W, only 5% of these devices can switching at any time, assuming that nothing else dissipates power. Assume optimistically that we can design FETs (Dual- Gate, FinFet, or whatever) that operate at 1 kW/cm 2 for FO4 = 10 ps and V DD = 0.6 V [Frank, Proc. IEEE, 3/01]  For a 2cm x 2cm high-performance microprocessor die, this means 4kW power dissipation.  If die power has to be limited to 200W, only 5% of these devices can switching at any time, assuming that nothing else dissipates power. [Ref: S. Borkar, Intel]

34 Low Power Design Essentials © An Era of Power-Limited Technology Scaling Technology innovations offer some relief –Devices that perform better at low voltage without leaking too much But also are adding major grieve –Impact of increasing process variations and various failure mechanisms more pronounced in low-power design regime. Most plausible scenario –Circuit and system level solutions essential to keep power/energy dissipation in check –Slow down growth in computational density, and use obtained slack to control power density increase. –Introduce design techniques to operate circuit at nominal, not worst-case, conditions

35 Low Power Design Essentials © Some Useful References … Selected Keynote Presentations  Fred Boekhorst, ”Ambient intelligence, the next paradigm for consumer electronics: How will it affect Silicon?, ” Digest of Technical Papers ISSCC, pp , Febr. 02.  Theo A. C. M. Claasen, “High speed: Not the only way to exploit the intrinsic computational power of silicon,” Digest of Technical Papers ISSCC, pp , Febr. 99.  Hugo De Man, “Ambient intelligence: Gigascale dreams and nanoscale realities,” Digest of Technical Papers ISSCC, pp , Febr. 05.  Patrick P. Gelsinger, Microprocessors for the new millennium: Challenges, opportunities, and new frontiers,” Digest of Technical Papers ISSCC, pp , Febr. 01.  Gordon E. Moore, “No exponential is forever: But "Forever" can be delayed!,” Digest of Technical Papers ISSCC, pp , Febr. 03.  Yrjö Neuvo, ”Cellular phones as embedded systems,” Digest of Technical Papers ISSCC, pp , Febr. 04.  Takayasu Sakurai, ”Perspectives on power-aware electronics,” Digest of Technical Papers ISSCC, pp , Febr. 03.  Robert Yung, Stefan Rusu, and Ken Shoemaker, Future trend of microprocessor design, Proceedings ESSCIRC, Sept Books and Book Chapters  S. Roundy, P. Wright and J.M. Rabaey, "Energy Scavenging for Wireless Sensor Networks," Kluwer Academic Publishers,  F. Snijders, “Ambient Intelligence Technology: An Overview,” In Ambient Intelligence, Ed. W. Weber et al, pp , Springer,  T. Starner and J. Paradiso, “Human-Generated Power for Mobile Electronics,” in “Low-Power Electronics”, C. Piguet, Editor, pp , CRC Press 05.

36 Low Power Design Essentials © Some Useful References (cntd) Publications  A. Bar-Cohen, S. Prstic, K. Yazawa, M. Iyengar. “Design and Optimization of Forced Convection Heat Sinks for Sustainable Development”, Euro Conference –New and Renewable Technologies for Sustainable,  S. Borkar, numerous presentations over the past decade …  R. Chu, “The Challenges of Electronic Cooling: Past, Current and Future,” Journal of Electronic Packaging, Vol 126, pp. 491, Dec  D. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proceedings of the IEEE, Volume 89, Issue 3, pp. 259 – 288, March  International Technology Roadmap for Semiconductors,  J. Markoff and S. Hansell, “Hiding in Plain Sight, Google Seeks More Power”, NY Times, June  R. Nowak, “A DARPA Perspective on Small Fuel Cells for the Military,” presented at Solid State Energy Conversion Alliance (SECA) Workshop, Arlington, March  J. Rabaey et al. "PicoRadios for wireless sensor networks: the next challenge in ultra-low power design,” Proc IEEE ISSCC Conference, pp.200-1, San Francisco, February  R. Schmidt, “Power Trends in the Electronics Industry – Thermal Impacts,” ACEED03, IBM Austin Conference on Energy-Efficient Design,  Toshiba, “Toshiba Announces World's Smallest Direct Methanol Fuel Cell With Energy Output of 100 Milliwatts,” June 2004.http://www.toshiba.co.jp/about/press/2004_06/pr2401.htm


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