ECE 425 Spring 2007Lecture 1 - Course Overview4 Course Objectives Students should be able to… VLSI Circuit Analysis: Understand MOS transistor operation, design eqns. Understand parasitics & perform simple calculations Understand static & dynamic CMOS logic Estimate delay of CMOS gates, networks, & long wires Estimate power consumption Understand design and operation of latches & flip/flops CMOS Processing and Layout Understand the VLSI manufacturing process. Have an appreciation of current trends in VLSI manufacturing. Understand layout design rules. Design and analyze layouts for simple digital CMOS circuits Design and analyze hierarchical circuit layouts. Understand ASIC Layout styles.
ECE 425 Spring 2007Lecture 1 - Course Overview5 Course Objectives Students should be able to… (cont’d) VLSI System Design Understand register-transfer level design. Design simple combinational and sequential logic circuits using using a Hardware Description Language (HDL). Design small to medium circuits consisting of multiple components such as a controller and datapath using a HDL. Understand the design flows used in industrial IC design. Design a small standard-cell chip in its entirety using a variety of CAD tools and check it for correct operation.
ECE 425 Spring 2007Lecture 1 - Course Overview7 Administrative Details Grading Take-Home Entry Exam 0% 2 In-Class Exams50% Laboratory40% Homeworks10% My Schedule ECE 425MWF 9:00-9:50, T 1:10-4:00 PM VAST 200MW 10:00-11:50 Office HoursMWF 2-3, T or by appointment
ECE 425 Spring 2007Lecture 1 - Course Overview8 Adminstrative Details (cont’d) Prerequisites ECE Intro. Solid State Devices & Circuits Unofficial: ECE 211, Digital Design Textbook W. Wolf, Modern VLSI Design: Systems on Silicon, 3rd. ed. Prentice-Hall, References J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd. ed., Prentice-Hall, N. Weste and D. Harris, CMOS VLSI Design: Addison-Wesley, M. Ciletti, Modeling, Synthesis, and Prototyping with the Verilog HDL, Prentice-Hall, 1999.
ECE 425 Spring 2007Lecture 1 - Course Overview9 VLSI Overview Common technologies CMOS Transistors & Logic Gates Structure “Switch-Level” Transistor Model Basic gates The VLSI Design Process Levels of Abstraction Design steps Design styles VLSI Trends
ECE 425 Spring 2007Lecture 1 - Course Overview12 VLSI Technology - CMOS Transitors What they really look like - a 130nm transistor from the IBM G5 processor: Image Source: Apple Computer
ECE 425 Spring 2007Lecture 1 - Course Overview13 Transistor Switch Model nfet or n transistor on when gate H "good" switch for logic L "poor" switch for logic H "pull-down" device pfet or p transistor on when gate L "good" switch for logic H "poor" switch for logic L "pull-up" device
ECE 425 Spring 2007Lecture 1 - Course Overview14 CMOS Logic Design Complementary transistor networks Pullup: p transistors Pulldown - n transistors
ECE 425 Spring 2007Lecture 1 - Course Overview18 The VLSI Design Process Move from higher to lower levels of abstraction Use CAD tools to automate parts of the process Use hierarchy to manage complexity Different design styles trade off: Design time Non-recurring engineering (NRE) cost Unit cost Performance Power Consumption
ECE 425 Spring 2007Lecture 1 - Course Overview19 VLSI Design Tradeoffs Non-Recurring Engineering (NRE) Costs Design Costs Mask “Tooling” costs Unit Cost - related to chip size Amount of logic Current technology Performance Clock speed Implementation Power consumption Power supply voltage Clock speed
ECE 425 Spring 2007Lecture 1 - Course Overview21 Full Custom Design Style Each circuit element carefully “handcrafted” Tradeoffs High Design Costs (huge effort!) High NRE Cost High Performance Low Unit Cost (good for high volume products!) Examples Analog and Mixed-Signal Microprocessor
ECE 425 Spring 2007Lecture 1 - Course Overview22 ASIC Design Style Pre-designed (or pre-manufactured) components that are assembled and wired by CAD tools. Standard cell (pre-designed cells) Gate array (pre-manufactured cells - just add wiring) Structured ASIC (complex function customized by wiring) Tradeoffs Low Design Cost High NRE Cost (lower in Gate Array / Structured ASIC) Medium Unit Cost Medium Performance Examples: Control chip for cell phone Graphics chips for desktop computers (e.g. nVidia, ATI)
ECE 425 Spring 2007Lecture 1 - Course Overview23 Programmable Logic Design Style Pre-manufactured components with programmable interconnect wired by CAD tools Tradeoffs Low Design Cost Low NRE Cost (basically 0) Low performance High unit cost Examples Network routers (e.g., Cisco) Gibson “digital” electric guitar
ECE 425 Spring 2007Lecture 1 - Course Overview24 System-on-a-chip Design Style Idea: combine several blocks Intellectual property (IP) cores (e.g. ARM processor) ASIC logic for special-purpose hardware Programmable Logic (PLD, FPGA) Analog Tradeoffs Medium design cost High NRE cost Medium performance Medium unit cost Examples Consumer electronics (e.g., iPod) Cable set-top boxes Sigmatel STMP3520 MP3 Decoder Image source: Semiconductor Insights, Inc.
ECE 425 Spring 2007Lecture 1 - Course Overview25 Perspective on Design Styles Few engineers will design custom chips Some engineers will design ASICs & SOCs Many engineers will design FPGA systems
ECE 425 Spring 2007Lecture 1 - Course Overview26 VLSI Trends: Moore’s Law In 1965, Gordon Moore predicted that transistors would continue to shrink, allowing: Doubled transistor density every months Doubled performance every months History has proven Moore right But, is the end is in sight? Physical limitations Economic limitations No exponential is forever, BUT Gordon Moore Intel Co-Founder and Chairmain Emeritus Image source: Intel Corporation Your job is to postpone “forever”!
ECE 425 Spring 2007Lecture 1 - Course Overview27 Microprocessor Trends (Intel) Source: media reportshttp://www.intel.com/pressroom/kits/quickreffam.htm “Deep Submicron”
ECE 425 Spring 2007Lecture 1 - Course Overview32 Summary - Technology Trends Processor Logic capacityincreases ~ 30% per year Clock frequencyincreases ~ 20% per year Cost per functiondecreases ~20% per year Memory DRAM capacity: increases ~ 60% per year (4x every 3 years) Speed: increases ~ 10% per year Cost per bit: decreases ~25% per year Not any more!
ECE 425 Spring 2007Lecture 1 - Course Overview33 Gallery - Early Processors Mos Technology 6502 Intel 4004 First µP xtors L=10µm
ECE 425 Spring 2007Lecture 1 - Course Overview35 Gallery - Current Processors Intel Core 2 Duo “Conroe” 291M transistors / 2.67GHz / 65W L=65nm Area=143mm 2 Image courtesy Intel Corporations All Rights Reserved
ECE 425 Spring 2007Lecture 1 - Course Overview36 Gallery - Current Processors Image courtesy International Business Machines All Rights Reserved IBM Cell Processor 234M transistors / 2GHz / ??W L=90nm Area=221mm 2
ECE 425 Spring 2007Lecture 1 - Course Overview37 Gallery - Current FPGA Xilinx Virtex FPGA