Does Cache Coherence solve it? Did load bring in an old value? Sum += A[i] is ___________ –Atomic – operation occurs in one unit, and nothing may interrupt it.
Synchronization Problem Reading and writing memory is a non-atomic operation –You can not read and write a memory location in a single operation We need __________________ that allow us to read and write without interruption
Solution Software Solution –“lock” – –“unlock” – Hardware –Provide primitives that read & write in order to implement lock and unlock
Software Using lock and unlock Sum += A[i]
Hardware Implementing lock & unlock Swap$1, 100($2) –Swap the contents of $1 and M[$2+100]
Hardware: Implementing lock & unlock with swap Lock: Li$t0, 1 Loop:swap $t0, 0($a0) bne$t0, $0, loop Unlock: sw $0, 0($a0) If lock has 0, it is free If lock has 1, it is held
Summary Cache coherence must be implemented for shared memory to work False sharing causes bad cache performance Hardware primitives necessary for synchronizing shared data