Download presentation

Presentation is loading. Please wait.

Published byJayden Romero Modified over 3 years ago

1
Cs 1110 Ch 4-1 Combinational Logic

2
° Introduction Logic circuits for digital systems may be: °2°2 combinational sequential OR A combinational circuit consists of logic gates; whose outputsat anytime are determined from only the present combination of inputs. A Sequential circuits contain memory elements ; the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs

3
A combinational circuits °4°4 °Specific functions °Adders, subtractors, comparators, decoders, encoders, andmultiplexers Combinational circuits Output Input

4
°Need to formulate circuits from problem descriptions 1.Determine number of inputs and outputs 2.Determine truth table format 3.Determine K-map 4.Determine minimal SOP 5.Determine Gate draw Implementations> oThere may be multiple outputs per design oSolve each output separately Design Procedure:

5
°Addition and subtraction of binary data is fundamental Need to determine hardware implementation °Represent inputs and outputs Inputs: single bit values, carry in Outputs: Sum, Carry °Hardware features Create a single-bit adder and chain together Binary Adders and Subtractors

6
Half Adder CABS 0001 A 0 B 0 S 0 C 1 0 0 0 1 1 0 1 0 1 1 0 1 Dec Binary 1 1 +1 2 10 °Add two binary numbers A 0, B 0 -> single bit inputs S 0 -> single bit sum C 1 -> carry out Half-Adder (HA), a 2-input bit-wise addition functional block. Circuit diagram Block diagram C S

7
Functional Block: Half Adder °A 2-input, 1-bit width binary adder that performs the following computations: °A half adder adds two bits to produce a two-bit sum °The sum is expressed as a sum bit, S and a carry bit, C °The half adder can be specified as a truth table for S and C X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 1 1 0 X Y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0

8
Logic Simplification: Half Adder °The K-Map for S, C is: °This is a pretty trivial map! By inspection: °and °These equations lead to several implementations. Y X 01 32 1 1 S Y X 01 32 1 C )YX()YX(S YXYXYXS )(C YXC )YX(

9
Implementations: Half Adder °The most common half adder implementation is: (e) YXC YXS X Y C S

10
Full Adder °Full adder includes carry in C i Note: 2 out-puts Full-Adder (FA), a 3-input bit-wise addition functional block. Note: 3 inputs

11
Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 SiSi °Full adder includes carry in C i °Notice interesting pattern in Karnaugh map. Note: 3 inputs

12
Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 S i =!C i !A i B i +!C i A i !B i +C i !A i !B i +C i A i B i °Full adder includes carry in C i °Alternative to XOR implementation °Reduce and/or representations into XORs S i = !C i !A i B i + !C i A i !B i + C i !A i !B i + C i A i B i S i = !C i !A i B i + A i !B i ) + C i (!A i !B i + A i B i ) S i = !C i (A i B i ) + C i !(A i B i ) S i = C i (A i B i )

13
Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 1 111 CiCi AiBiAiBi 00011110 0 1 C i+1 °Now consider implementation of carry out °Two outputs per full adder bit (C i+1, S i ) Note: 3 inputs

14
Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = A i B i + C i B i + C i A i °Now consider implementation of carry out °Minimize circuit for carry out - C i+1

15
Full Adder C i+1 = A i B i + C i !A i B i + C i A i !B i C i+1 = A i B i + C i (!A i B i + A i !B i ) C i+1 = A i B i + C i (A i B i ) Recall: S i = C i (A i B i ) C i+1 = A i B i + C i (A i B i )

16
Full Adder S i = C i (A i B i ) Half-adder C i+1 = A i B i + C i (A i B i ) °Full adder made of several half adders

17
Full Adder A full adder can be made from two half adders (plus an OR gate). °Hardware repetition simplifies hardware design

18
Full Adder Block Diagram °Putting it all together Single-bit full adder Common piece of computer hardware

19
Full Adder °How to design circuit to add 2 bits? 2-bit Adder °4 bit? 4- bit Adder °8 bit ? 8-bit Adder °By using chain of one-bit Adder??!!

20
4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0 °Chain single-bit adders together. °What does this do to delay? °The approach is call ripple-carry addition Can be slow for large designs

Similar presentations

OK

Module 9. Digital logic circuits can be categorized based on the nature of their inputs either: Combinational logic circuit It consists of logic gates.

Module 9. Digital logic circuits can be categorized based on the nature of their inputs either: Combinational logic circuit It consists of logic gates.

© 2018 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google