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Cs 1110 Ch 4-1 Combinational Logic

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° Introduction Logic circuits for digital systems may be: °2°2 combinational sequential OR A combinational circuit consists of logic gates; whose outputsat anytime are determined from only the present combination of inputs. A Sequential circuits contain memory elements ; the outputs are a function of the current inputs and the state of the memory elements the outputs also depend on past inputs

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A combinational circuits °4°4 °Specific functions °Adders, subtractors, comparators, decoders, encoders, andmultiplexers Combinational circuits Output Input

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°Need to formulate circuits from problem descriptions 1.Determine number of inputs and outputs 2.Determine truth table format 3.Determine K-map 4.Determine minimal SOP 5.Determine Gate draw Implementations> oThere may be multiple outputs per design oSolve each output separately Design Procedure:

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°Addition and subtraction of binary data is fundamental Need to determine hardware implementation °Represent inputs and outputs Inputs: single bit values, carry in Outputs: Sum, Carry °Hardware features Create a single-bit adder and chain together Binary Adders and Subtractors

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Half Adder CABS 0001 A 0 B 0 S 0 C 1 0 0 0 1 1 0 1 0 1 1 0 1 Dec Binary 1 1 +1 2 10 °Add two binary numbers A 0, B 0 -> single bit inputs S 0 -> single bit sum C 1 -> carry out Half-Adder (HA), a 2-input bit-wise addition functional block. Circuit diagram Block diagram C S

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Functional Block: Half Adder °A 2-input, 1-bit width binary adder that performs the following computations: °A half adder adds two bits to produce a two-bit sum °The sum is expressed as a sum bit, S and a carry bit, C °The half adder can be specified as a truth table for S and C X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 1 1 0 X Y C S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0

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Logic Simplification: Half Adder °The K-Map for S, C is: °This is a pretty trivial map! By inspection: °and °These equations lead to several implementations. Y X 01 32 1 1 S Y X 01 32 1 C )YX()YX(S YXYXYXS )(C YXC )YX(

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Implementations: Half Adder °The most common half adder implementation is: (e) YXC YXS X Y C S

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Full Adder °Full adder includes carry in C i Note: 2 out-puts Full-Adder (FA), a 3-input bit-wise addition functional block. Note: 3 inputs

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 SiSi °Full adder includes carry in C i °Notice interesting pattern in Karnaugh map. Note: 3 inputs

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 S i =!C i !A i B i +!C i A i !B i +C i !A i !B i +C i A i B i °Full adder includes carry in C i °Alternative to XOR implementation °Reduce and/or representations into XORs S i = !C i !A i B i + !C i A i !B i + C i !A i !B i + C i A i B i S i = !C i !A i B i + A i !B i ) + C i (!A i !B i + A i B i ) S i = !C i (A i B i ) + C i !(A i B i ) S i = C i (A i B i )

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 1 111 CiCi AiBiAiBi 00011110 0 1 C i+1 °Now consider implementation of carry out °Two outputs per full adder bit (C i+1, S i ) Note: 3 inputs

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Full Adder 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = A i B i + C i B i + C i A i °Now consider implementation of carry out °Minimize circuit for carry out - C i+1

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Full Adder C i+1 = A i B i + C i !A i B i + C i A i !B i C i+1 = A i B i + C i (!A i B i + A i !B i ) C i+1 = A i B i + C i (A i B i ) Recall: S i = C i (A i B i ) C i+1 = A i B i + C i (A i B i )

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Full Adder S i = C i (A i B i ) Half-adder C i+1 = A i B i + C i (A i B i ) °Full adder made of several half adders

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Full Adder A full adder can be made from two half adders (plus an OR gate). °Hardware repetition simplifies hardware design

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Full Adder Block Diagram °Putting it all together Single-bit full adder Common piece of computer hardware

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Full Adder °How to design circuit to add 2 bits? 2-bit Adder °4 bit? 4- bit Adder °8 bit ? 8-bit Adder °By using chain of one-bit Adder??!!

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4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0 °Chain single-bit adders together. °What does this do to delay? °The approach is call ripple-carry addition Can be slow for large designs

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08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

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