2. Lecture 12: Machine Processing Intro to IT COSC1078 Introduction to Information Technology Lecture 12 Machine Processing James Harland james.harland@rmit.edu.au

3. Lecture 12: Machine ProcessingIntro to IT Introduction James Harland Email: james.harland@rmit.edu.au URL: www.cs.rmit.edu.au/~jah Phone: 9925 2045 Office: 14.10.1 Consultation: Mon 4.30-5.30, Thu 11.30-12.30 What colour is my office door? Carpet? Chair?

4. Lecture 12: Machine ProcessingIntro to IT Introduction to IT 1 Introduction 2 Images 3 Audio 4 Video WebLearnTest 1 5 Binary Representation Assignment 1 6 Data Storage 7 Machine Processing 8 Operating Systems WebLearn Test 2 9 Processes Assignment 2 10 Internet 11 Internet Security WebLearn Test 3 12 Future of ITAssignment 3, Peer and Self Assessment

5. Lecture 12: Machine ProcessingIntro to IT Overview  Questions?  Assignments 1 & 2  Machine Processing  Questions?

6. Lecture 12: Machine ProcessingIntro to IT Assignments 1& 2 Assignment 1  Currently being marked  Will have marks out next week Assignment 2  Specification has been published  Must be done in groups of 2 or 3  Can change groups from Assignment 1 (if you wish)  Must have a blog on Blackboard

7. Lecture 12: Machine ProcessingIntro to IT What do computers do?  Compute!  Input/Output  Processing  Memory

8. Lecture 12: Machine ProcessingIntro to IT Moore’s Law “Processor speed doubles about every 18 months” -- Gordon Moore, Intel co-founder, 1965  Intended for period 1965-1975  Held true ever since 1965!  Must end sometime …

9. Lecture 12: Machine ProcessingIntro to IT Moore’s Law

10. Lecture 12: Machine ProcessingIntro to IT Moore’s Law

11. Lecture 12: Machine ProcessingIntro to IT Memory  Memory differs in performance and cost  Processor is typically much faster than memory

12. Lecture 12: Machine ProcessingIntro to IT Memory  Arranged as a hierarchy of cache Level 1 Level 2 Level 3 Main Memory

13. Lecture 12: Machine ProcessingIntro to IT Processing ALU CPU BUS REGISTERS MEMORY

14. Lecture 12: Machine ProcessingIntro to IT Machine Instructions 1.Move first value from memory into register 1 2.Move second value from memory into register 2 3.If register 2 is zero, go to Step 6 4.Divide register 1 by register 2 & store result in register 3 5.Store register 3 value in memory 6.Stop “Divide two numbers”

15. Lecture 12: Machine ProcessingIntro to IT Machine Instructions 1.LOAD register 1 from memory 2.LOAD register 2 from memory 3.JUMP to Step 6 if register 2 is zero 4.Divide register 1 by register 2 and store result in register 3 5.STORE register 3 value in memory 6.Stop

16. Lecture 12: Machine ProcessingIntro to IT Instructions in Binary? 01010100001010101010100110100010101001101001010010 100011100010101010100101111001001010… LOAD register 1 LOAD register 2 JUMP …. STORE …. 10101100 10110011 00010010 00110011 00111111 MEMORY

17. Lecture 12: Machine ProcessingIntro to IT One Scheme 16-bit operation codes (simple example) Operation Code (4 bits) Operand (12 bits) Represent as 4 Hexadecimal numbers (0-9,A-F) Each instruction is two bytes long

18. Lecture 12: Machine ProcessingIntro to IT One Scheme 156C LOAD register 5 from memory 6C 166D LOAD register 6 from memory 6D 5056 ADD register 5 & 6 & store in register 0 306E STORE register 0 to memory 6E C000 HALT.... (up to 2 16 = 65,536 different instructions)

19. Lecture 12: Machine ProcessingIntro to IT Fetch Decode Execute FETCH EXECUTEDECODE Machine cycle

20. Lecture 12: Machine ProcessingIntro to IT Fetch Decode Execute FETCH EXECUTEDECODE Machine cycle

21. Lecture 12: Machine ProcessingIntro to IT Two special registers Instruction register: holds current instruction Program counter: address of next instruction Fetch: Put instruction specified by program counter into instruction register Increment program counter by two Decode: Work out what to do Execute: Perform the instruction

22. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A0 AddressContents

23. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A0 FETCH 156C

24. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 FETCH 156C

25. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 DECODE 156C 6C 2B

26. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 EXEC 156C 6C 2B 2B5

27. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 FETCH 166D

28. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 FETCH 166D

29. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 DECODE 166D

30. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 EXEC 166D 6D FF FF6

31. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A6 FETCH 5056

32. Lecture 12: Machine ProcessingIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register …

33. Lecture 12: Machine ProcessingIntro to IT Processing Program Counter Instruction Register EXEC B258 B4

34. Lecture 12: Machine ProcessingIntro to IT Processing Program Counter Instruction Register EXEC B258 58

35. Lecture 11: Machine ProcessingIntro to IT Processing  Jump instructions change program counter  Can load any memory address into program counter (!!!)  Often use pipelining for efficiency  Fetch next instruction while executing  Processor doesn’t wait for fetch to complete  Can do more than one instruction …

36. Lecture 12: Machine ProcessingIntro to IT Connecting devices ??

37. Lecture 12: Machine ProcessingIntro to IT Universal Serial Bus (USB)

38. Lecture 12: Machine ProcessingIntro to IT Memory-mapped I/O Program Counter Instruction Register C4 EXEC 3634 34 FF FF6 Just like writing to a memory address

39. Lecture 12: Machine ProcessingIntro to IT Direct Memory Access (DMA) Put some data in memory! OK

40. Lecture 12: Machine ProcessingIntro to IT Direct Memory Access Direct Memory Access means that doesn’t have to wait for the

41. Lecture 12: Machine ProcessingIntro to IT What are these? Firewirebottleneck bandwidthhandshakeParallel port Serial port

42. Lecture 12: Machine ProcessingIntro to IT Busy Bertie the bus … Von Neumann bottleneck

43. Lecture 12: Machine ProcessingIntro to IT Conclusion  Work on Assignment 2  Finish reading book!