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Lecture 5 EGRE 254 1/28/09

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2 Boolean algebra a.k.a. “switching algebra” –deals with Boolean values -- 0, 1 Positive-logic convention –analog voltages LOW, HIGH --> 0, 1 Negative logic -- seldom used Signal values denoted by variables (X, Y, FRED, etc.)

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3 Boolean operators Complement:X or (opposite of X) AND:X Y OR:X + Y binary operators, described functionally by truth table.

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4 More definitions Literal: a variable or its complement –X, X, FRED, CS_L Expression: literals combined by AND, OR, parentheses, complementation –X+Y –P Q R –A + B C –((FRED Z) + CS_L A B C + Q5) RESET Equation: Variable = expression –P = ((FRED Z) + CS_L A B C + Q5) RESET

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5 Logic symbols

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6 Basic Axioms A1A1’ A2A2’ A3A3’ A4A4’ A5A5’

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7 Proving theorems Using axioms or theorems already proven. Perfect induction – Verify theorem for all possible values of the variables. 1 variable 2 = 2 1 possible values. 0, 1 2 variables 4 = 2 2 possible values. 00, 01, 10, 11 3 variables 8 = 2 3 possible values. 000, 001, …, 111 n variables 2 n possible values. For general case of n variable we use the mathematical technique of finite induction.

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8 Prove T1 and T1’ T1 : X + 0 = X Proof 1a –If X = 0 then X + 0 = X by A4’ –If X = 1 then X + 0 = X by A5’ Proof 2a,b T1’: X 1 = X Proof 1b –If X = 1 then X 1= X by A4 –If X = 0 then X 1= X by A5 Proof 3b –T1’ follows from duality of T1. XX+0 X1X1 000 111

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9 Basic Theorems T1T1’ T2T2’ T3 Idempotent law T3’ T4T4’Same as T4 T5T5’

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10 Theorems T6 Commutative law T6’ T7 Associative law T7’ T8 Distributive law T8’ T9 Adsorption law T9’ T10 T10’ T11 T11’

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11 T8’ Not what we would expect! Proof 1: using truth table (perfect induction) XYZX+YX+ZYZ(X+Y)(X+Z)X + YZ 00000000 00101000 01010000 01111111 10011011 10111011 11011011 11111111

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12 T8’ Proof 2: Algebraically using proved theorems (X + Y)(X + Z) = (X+Y)X +(X+Y)Z ;Why? = XX+YX+XZ+YZ ; T6’, T8 = X+XY+XZ+YZ ; T3’, T6’ = X 1 + X(Y+Z) + YZ ; T1’, T8 = X(1+(Y+Z)) + YZ ; T8 = X 1 + YZ ; T6, T1’ = X + YZ ; T1’ Better (X + Y)(X + Z) = X + XZ + XY + YZ = X(1+Z+Y) + YZ = X + YZ Proof 3: Follows from T8 and duality.

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13 Algebraic Proofs T10: XY+XY’ = X(Y+Y’) = X 1 = X T10’: (X+Y)(X+Y’) = X+XY+XY’+YY’ = X(1+Y+Y’) + 0 = X(1) = X T11: XY+X’Z+YZ = XY+X’Z+(XYZ+X’YZ) = XY(1+Z) + X’Z(1+Z) = XY + X’Z T11’: Do as an exercise.

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14 Example using T9 (A+B)’C + (A+B)’CD’(E+F) = (A+B)’C – Treat (A+B)’C as X, treat D’(E+F) as Y Or instead of using T9 recognize that (A+B)’C + (A+B)’CD’(E+F) = (A+B)’C(1+D’(E+F)) = (A+B)’C It is not necessary to memorize all of these theorems. –Know through T5’ and couple that with your knowledge of ordinary algebra.

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15 XOR X Y = XY’ + X’Y X 0 = X X 1 = X’ X X = 0 X X’ = 1 X Y Z = X (Y Z) = Z X Y XY XYXY 000 011 101 110

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16 How are these XOR gates used?

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17 DeMorgan’s Theorem These are the equations you must memorize But notice that given one it is trivial to obtain the others.

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18 Prove XYX’Y’X’Y’X+Y(X+Y)’ 0011101 0110010 1001010 1100010 Alternative proof. Let X = 0 then 1Y’ = (0 + Y)’ Let X = 1, then 0Y’ = (1+Y)’ = 1’ = 0

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19 DeMorgans Theorem in n variables

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20 Generalizations DeMorgan’s Theorem Duality. If then

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22 Shannon’s expansion theorem Proof: Consider f(x i ) = x i ’f(0) xi + x i f(1) xi When x i = 0 then f(0) xi = 1f(0) xi + 0f(1) xi = f(0) xi When x i = 1 then f(1) xi = 0f(0) xi + 1f(1) xi = f(1) xi Thus, by perfect induction f(x i ) = x i ’f(0) xi + x i f(1) xi

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23 Implementation example Draw circuit directly from equations. Draw circuit using only NAND gates.

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24 Design example Design a 3-input majority circuit XYZF 000 001 010 011 100 101 110 111

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25 Design example Design a 3-input majority circuit XYZF 0000 0010 0100 0111 1000 1011 1101 1111

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26 Design example Design a 3-input majority circuit

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27 Design example Design a 3-input majority circuit XYZF 0000 0010 0100 0111 1000 1011 1101 1111

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28 Design example Design a 3-input majority circuit

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29 Example Show how to build an 8 input and gate using several two input and gates. Which is better? Why?

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30 Schmitt-trigger gates contain input hysteresis. Useful for interfacing to slow or noisy signals.

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32 Tri-state buffers

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