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William Stallings Computer Organization and Architecture Chapter 14 Control Unit Operation.

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Presentation on theme: "William Stallings Computer Organization and Architecture Chapter 14 Control Unit Operation."— Presentation transcript:

1 William Stallings Computer Organization and Architecture Chapter 14 Control Unit Operation

2 Micro-Operations zA computer executes a program zFetch/execute cycle zEach cycle has a number of steps ysee pipelining zCalled micro-operations zEach step does very little zAtomic operation of CPU

3 Constituent Elements of Program Execution

4 Fetch - 4 Registers zMemory Address Register (MAR) yConnected to address bus ySpecifies address for read or write op zMemory Buffer Register (MBR) yConnected to data bus yHolds data to write or last data read zProgram Counter (PC) yHolds address of next instruction to be fetched zInstruction Register (IR) yHolds last instruction fetched

5 Fetch Sequence zAddress of next instruction is in PC zAddress (MAR) is placed on address bus zControl unit issues READ command zResult (data from memory) appears on data bus zData from data bus copied into MBR zPC incremented by 1 (in parallel with data fetch from memory) zData (instruction) moved from MBR to IR zMBR is now free for further data fetches

6 Fetch Sequence (symbolic) zt1:MAR <- (PC) zt2:MBR <- (memory) z PC <- (PC) +1 zt3:IR <- (MBR) z(tx = time unit/clock cycle) zor zt1:MAR <- (PC) zt2:MBR <- (memory) zt3:PC <- (PC) +1 zIR <- (MBR)

7 Rules for Clock Cycle Grouping zProper sequence must be followed yMAR <- (PC) must precede MBR <- (memory) zConflicts must be avoided yMust not read & write same register at same time yMBR <- (memory) & IR <- (MBR) must not be in same cycle zAlso: PC <- (PC) +1 involves addition yUse ALU yMay need additional micro-operations

8 Indirect Cycle zMAR <- (IR address ) - address field of IR zMBR <- (memory) zIR address <- (MBR address ) zMBR contains an address zIR is now in same state as if direct addressing had been used z(What does this say about IR size?)

9 Interrupt Cycle zt1:MBR <-(PC) zt2:MAR <- save-address z PC <- routine-address zt3:memory <- (MBR) zThis is a minimum yMay be additional micro-ops to get addresses yN.B. saving context is done by interrupt handler routine, not micro-ops

10 Execute Cycle (ADD) zDifferent for each instruction ze.g. ADD R1,X - add the contents of location X to Register 1, result in R1 zt1:MAR <- (IR address ) zt2:MBR <- (memory) zt3:R1 <- R1 + (MBR) zNote no overlap of micro-operations

11 Execute Cycle (ISZ) zISZ X - increment and skip if zero yt1:MAR <- (IR address ) yt2:MBR <- (memory) yt3:MBR <- (MBR) + 1 yt4:memory <- (MBR) y if (MBR) == 0 then PC <- (PC) + 1 zNotes: yif is a single micro-operation yMicro-operations done during t4

12 Execute Cycle (BSA) zBSA X - Branch and save address yAddress of instruction following BSA is saved in X yExecution continues from X+1 yt1:MAR <- (IR address ) y MBR <- (PC) yt2:PC <- (IR address ) y memory <- (MBR) yt3:PC <- (PC) + 1

13 Functional Requirements zDefine basic elements of processor zDescribe micro-operations processor performs zDetermine functions control unit must perform

14 Basic Elements of Processor zALU zRegisters zInternal data pahs zExternal data paths zControl Unit

15 Types of Micro-operation zTransfer data between registers zTransfer data from register to external zTransfer data from external to register zPerform arithmetic or logical ops

16 Functions of Control Unit zSequencing yCausing the CPU to step through a series of micro- operations zExecution yCausing the performance of each micro-op zThis is done using Control Signals

17 Control Signals (1) zClock yOne micro-instruction (or set of parallel micro- instructions) per clock cycle zInstruction register yOp-code for current instruction yDetermines which micro-instructions are performed

18 Control Signals (2) zFlags yState of CPU yResults of previous operations zFrom control bus yInterrupts yAcknowledgements

19 Control Signals - output zWithin CPU yCause data movement yActivate specific functions zVia control bus yTo memory yTo I/O modules

20 Example Control Signal Sequence - Fetch zMAR <- (PC) yControl unit activates signal to open gates between PC and MAR zMBR <- (memory) yOpen gates between MAR and address bus yMemory read control signal yOpen gates between data bus and MBR

21 Internal Organization zUsually a single internal bus zGates control movement of data onto and off the bus zControl signals control data transfer to and from external systems bus zTemporary registers needed for proper operation of ALU

22 Hardwired Implementation (1) zControl unit inputs zFlags and control bus yEach bit means something zInstruction register yOp-code causes different control signals for each different instruction yUnique logic for each op-code yDecoder takes encoded input and produces single output yn binary inputs and 2 n outputs

23 Hardwired Implementation (2) zClock yRepetitive sequence of pulses yUseful for measuring duration of micro-ops yMust be long enough to allow signal propagation yDifferent control signals at different times within instruction cycle yNeed a counter with different control signals for t1, t2 etc.

24 Problems With Hard Wired Designs zComplex sequencing & micro-operation logic zDifficult to design and test zInflexible design zDifficult to add new instructions

25 Required Reading zStallings chapter 14

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