7 Data Bus8088: AD0~AD78086: AD0~AD15Address Bus (24pins)8088: AD0~AD7, A8~A198086: AD0~AD15, A16~A19AD means address and data are commonly used and separated by mux.ALE: Address Latch Enable to latch address signals
8 NMI (nonmaskable interrupt), edge-triggered Pin DescriptionBHE (bus high enable): to distinguish between the low byte and high byte of data.NMI (nonmaskable interrupt), edge-triggeredINTR (interrupt request), active high level triggeredCLOCK, need accurate clock signalsRESET: after resetREADY: insert wait stateTest input from 8087What is 8087?CSFFFFHDS0000HSS0000FESIPFlagsClearQueueEmpty
9 Minimum/Maximum ModeMN/MX (pin 33) =5V to define pin 24 to pin 31Used for the 8085 series
10 Pins in maximum modeQS0 and QS1 (queue status, pins 24 and 25)S0, S1, and S2 (Status signals, pins 26, 27, and 28)
11 LOCK (pin 29)Used with “LOCK” prefix in the instruction to gain the control of the system bus (prevent DMA to control the bus when the instruction is under processing).LOCK MOV AX, DataRQ/GT0, RQ/GT1 (request/grant, pins 30, 31)These bidirectional pins allow another processor to gain control of the local bus.Pins in Minimum Mode
18 Section 1.3 8284 Clock Generator and Driver Input pins:RES (reset in)X1 and X2 (crystal in): must be three times the desired frequency. IBM PC is MHzF/C (frequency/clock select), select either the crystal input freq or EFI freqEFI (external frequency in)CSYNC (clock synchronization), allow several 8284 connected togetherRDY1 and AEN1, used as READY signal for inserting WAIT state.
19 RDY2 and AEN2, like RDY1 and AEN1 and are used for multiprocessing system. ASYNCOutput signalsRESETOSC (oscillator), provides the same frequency as the oscillator.CLK (clock), 1/3 of the crystal frequency and 33% duty cycleLCLOCK (peripheral clock), 1/2 CLK frequency, 50% duty cycleREADY, for inserting WAIT cycleDuty cycle?