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**Behavioral Modeling of Data Converters using Verilog-A**

George Suárez Graduate Student Electrical and Computer Engineering University of Puerto Rico, Mayaguez Code 564: Microelectronics and Signal Processing Branch NASA Goddard Space Flight Center

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**Agenda Introduction Verilog-A Objectives Sample and Hold Generic DAC**

Analysis Jitter Noise Thermal noise Model Simulation results Generic DAC Analysis and model Dynamic element matching

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**Agenda Generic ADC Flash ADC SAR ADC Pipelined ADC Analysis and model**

Simulation results Flash ADC SAR ADC Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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**Agenda ΣΔ ADC Conclusions Future Work Acknowledgements References**

1.5 bit MDAC Digital Correction Simulation results ΣΔ ADC ΣΔ Modulator SC integrator analysis Model Conclusions Future Work Acknowledgements References

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Introduction Transistor-level modeling and simulation is the most accurate approach for mixed-signal circuits. It becomes impractical for complex systems due to the long computational time required. Cell View No. of Transistors No. of Equations Simulation Time Transistor Level 436 1111 52 s 7000 17601 125 ks 1 day, 10 hours, 42 min. Taken form the article: Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A Nitin Mohan, Sirific Wireless

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Introduction This situation has led circuit designers to consider alternate modeling techniques: In addition, behavioral modeling can be effectively used in a top-down design approach. Approach Accuracy Speed Flexibility Device models Custom C++ models Finite-difference equations Circuit-based macromodels Time-domain macromodels Behavioral models Cell View No. of Transistors No. of Equations Simulation Time Transistor Level 436 1111 52 s Behavioral 270 697 4 s 7000 17601 125 ks 1 day, 10 hours, 42 min. 439 1148 124s Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A, Nitin Mohan, Sirific Wireless

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**Top-Down Design Approach**

Introduction Loop filter F(s) Phase comparator VCO A=1 fo A=1 System Level (Matlab, C++, SystemC, AHDLs, etc…) Behavioral models + - Vout Vin + - Functional Level (SPICE, AHDLs) V + V - Transistor Level (SPICE) Layout Top-Down Design Approach

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Verilog-A The Verilog-A is a high-level language developed to describe the structure and behavior of analog systems and their components. It is an extension to the IEEE 1364 Verilog HDL specification for digital design. The analog systems are described in Verilog-A in a modular way using hierarchy and different levels of modeling complexity. The motivation is to invest in a new higher level of abstraction in analog design and its combination with the digital one. `include "constants.vams" `include "disciplines.vams" module COMP (vin, vref, vout); output vout; electrical vout; input vin; electrical vin; input vref; electrical vref; parameter real slope = 100.0; parameter real offset = 0.0 ; vin vref vout

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Objectives Build a set of analog and mixed-signal behavioral models using the Verilog-A AHDL, that allows a high level simulation of ADCs. Simulate some popular ADCs architectures such as: Flash ADC SAR ADC Pipelined ADC Simulate other common used mixed-signal circuits such as: ΣΔ Modulator Sample and Hold Provide a general modeling approach for noise sources and other non-idealities. Provide performance results for the simulated data converters such as spectrum measures SNR, SNDR, THD etc.

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**Agenda Introduction Verilog-A Objectives Sample and Hold Generic DAC**

Analysis Jitter Noise Thermal noise Model Simulation results Generic DAC Analysis and model Dynamic element matching

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**Sample and Hold Φs1 δ Φs1 Cs Vin Vout 1 – exp[-t / (2RonCs)] - Cp**

+ - Vin Vout Cs Φs1 Ron 1 – exp[-t / (2RonCs)] Cp CL Thermal noise Vth ≈ kT/Cs (Opamp noise neglected) Φs1 Jitter δ x(t+δ) - x(t) ≈ δ x(t) εg= 1 - Cs /[ Cs + (Cs + Cp)/A0] Finite DC gain A0 Finite GBW Cp and CL Defective settling Linear Slewing Partial Slewing Vout Time Ideal value |H| f

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Jitter Noise Clock jitter is due to the non-uniform sampling of the input signal. The magnitude of this error is a function of the statistical properties of the jitter and the input signal to the system. In sampled data systems, when a sinusoidal input is taken, the error introduced by jitter can be modeled by, δ ΔV x(t+δ) - x(t) ≈ 2πfinδAcos(2πfinnt) ≈ δ x(t) where δ is the sampling uncertainty, this is taken to be a Gaussian random process with standard deviation Δt.

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Jitter Noise It is assumed that is a Gaussian random process with zero mean and standard deviation Δt. Δt -Δt Input signal to the system Statistical properties of the jitter

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Thermal Noise Thermal noise in circuits is because of the random fluctuation of carriers due to thermal energy. Proportional to the temperature. It is assumed to be a Gaussian random process with zero mean.

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**+ Sample and Hold model Thermal Noise Vin Vout Jitter τ = RonCs Vout**

Ideal S&H Filter Vin Vout + Defective settling Jitter τ = RonCs Ideal Nonideal Vout

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**Sample and Hold simulation results**

PSD for sampled signal of 0 dB, fin = MHz N = 8192, BW = 25MHz Increase in noise floor due nonidealities

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**Agenda Introduction Verilog-A Objectives Sample and Hold Generic DAC**

Analysis Jitter Noise Thermal noise Model Simulation results Generic DAC Analysis and model Dynamic element matching

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**Generic DAC + Mismatch in DAC units. INL Vout Gain error Offset … 2B-1**

Generic DAC model including mismatch in units 2B-1 1 2B-2 Thermometer decoder B bits Mismatch in capacitors! (trimming can reduced it to 0.1% Increase in harmonics content) MSB 27C 26C 22C 21C C Dummy Vin Vref Gnd - + SAR Capacitive DAC, SAH and comparator

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**Integral non-linearity**

Generic DAC model Integral non-linearity INL Quantization step q Gain error εg Full scale voltage FS Offset error εoff nominal gain g DAC with mismatch + N bits α offset xa wa va vadc Digital input code Analog output Ideal Nonideal Offset error = 0.5LSB α(wa + off) ya 1/(1+q εg) α (2N-1-1)q A FS/(2N-1) q (1- ε0)xa + xa3 ε0/A2 wa (INL)sqrt(27)/(2N-2) ε0 (l1 εg-εoff)q offset -FS/(2g) l1 Gain error = 0.5LSB INL = 0.5LSB

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DEM Dynamic Element Matching (DEM) techniques are used to minimize the effect of DAC units mismatch. DAC DEM techniques can be divided in deterministic and stochastic. Due to design complexity and non-scalability for modeling purposes it is easier to implement a general stochastic approach using randomization. Spread the mismatch error energy across the spectrum generating white or colored noise in the DAC output. Magnitude (dB) f (Hz) Improve the DAC performance by locating the distortion caused by the component mismatch errors in certain frequency bands. Magnitude (dB) f (Hz)

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**DEM simulation results**

unit … Vout + 2B-1 1 2B-2 Thermometer decoder B bits Randomize DAC 0.1% mismatch DEM off DEM on By randomizing the DAC units (i.e. using a digital circuitry FSM with a system clock) the effect of the mismatch in the spectrum is reduced by reducing the harmonic distortion. In Verilog-A its rather simple to randomize uniformly the units. Assuming we have a system clock, for each rising edge of the clock signal we randomize the units. if(DEM_enable) begin generate i(1,`DAC_UNITS) begin temp = $dist_uniform(seed, 1, `DAC_UNITS); if(temp - floor(temp) >= 0.5) DEM[i] = ceil(temp); else DEM[i] = floor(temp); end end // Then select units stored in the array DEM[ ] for conversion

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**Agenda Generic ADC Analysis and model Simulation results Flash ADC**

SAR ADC Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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**Integral non-linearity**

Generic ADC model Integral non-linearity INL Quantization step q Gain error εg Full scale voltage FS Offset error εoff nominal gain g α(wa + off) ya 1/(1+qεg) α (2N-1-1)q A FS/(2N-1) (1- ε0)xa + xa3 ε0/A2 wa (INL)sqrt(27)/(2N-2) ε0 (l1 εg-εoff)q offset -FS/(2g) + q/2 l1 Ideal ADC + N bits α offset xa wa va vadc Analog input Digital output code Ideal Nonideal Offset error = 0.5LSB Gain error = 0.5LSB INL = 0.5LSB

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**Generic ADC simulation results**

PSD plot for 8-bit generic ADC with 0 dB input signal fin of KHz, Samples = 8192, BW = 2MHz SNDR = dB SNR = dB THD = dB SFDR = dB ENOB = 8 bits SNDR = dB SNR = dB THD = dB SFDR = dB ENOB = 7.7 bits gain error =0.5LSB, offset error = 0.5LSB and INL = 0.5LSB

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**Agenda Generic ADC Analysis and model Simulation results Flash ADC**

SAR ADC Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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**Flash ADC … Are made by cascading high-speed comparators.**

+ - … +Vref -Vref R Decoder N bits Are made by cascading high-speed comparators. Are the fastest way to convert an analog signal to a digital signal. Ideal for applications requiring very large bandwidth. Typically consume more power than other ADC architectures and are generally limited to 8-bits resolution.

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**Flash ADC non-idealities**

OPAMP Finite DC gain Finite GBW Input resistance Output resistance Bias current Offset voltage Slew Rate Bubbles It is due the metastability of the comparators. (Future work will try model this effect) Cc V + V - Vdd Ibias CL GBW = gm1/CC I5 I5 = SR*Cc Cadence provides a well accepted behavioral model of an non-ideal OPAMP/OTA for the most used AHDLs (Verilog-A, Verilog-AMS and VHDL-AMS)!

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**Flash ADC simulation results**

PSD plot for 8-bit Flash ADC with 0 dB input signal fin of 3.01MHz, Samples = 4096, BW = 5MHz Ideal Nonideal SNDR (dB) 49.264 44.408 SNR (dB) 49.323 44.481 THD (dB) SFDR (dB) 60.778 47.261 ENOB 7.9 7.1

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**Agenda Generic ADC Analysis and model Simulation results Flash ADC**

SAR ADC Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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SAR ADC Successive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits) applications with sample rates under 5 Msps. Used in portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition. Provide low power consumption. An N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete.

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**SAR ADC Anti-aliased signal Timing control Sample Successive + & hold**

Approximation Register (SAR) DAC Timing control Sample & hold Start CLK EOC N bits Vin + - CONV SAH Conversion time Anti-aliased signal VDAC time Vin bit 3=0 bit 2=1 bit 1=0 bit 0=1 ¼ Vref ½ Vref ¾ Vref Vref (MSB) (LSB)

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**SAR 8-bit ADC simulation results**

Ideal PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of KHz, Samples = 8192, Bandwidth = 250KHz SNDR (dB) 49.823 SNR (dB) 49.949 THD (dB) SFDR (dB) 67.353 ENOB 8.0

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**SAR 8-bit ADC simulation results**

PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of KHz, Samples = 8192, Bandwidth = 250KHz Increase in harmonics due mismatch in DAC units Ideal SNDR 6.02N+1.76=49.92 dB

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**SAR 8-bit ADC simulation results**

PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of KHz, Samples = 8192, Bandwidth = 250KHz Increase in harmonics due mismatch in DAC units 7.3 6.9 ENOB 48.78 47.74 SFDR (dB) -66.38 -45.61 THD (dB) 45.99 47.43 SNR (dB) 45.95 43.42 SNDR (dB) Ideal SNDR 6.02N+1.76=49.92 dB

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**Agenda Generic ADC Analysis and model Simulation results Flash ADC**

SAR ADC Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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**Agenda Digital Correction Simulation results ΣΔ ADC ΣΔ Modulator**

1.5 bit MDAC Digital Correction Simulation results ΣΔ ADC ΣΔ Modulator SC integrator analysis Model Conclusions Future Work Acknowledgements References

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Pipelined ADC Has become the most popular ADC architecture for sampling rates from a few MS/s up to 100MS/s, with resolutions from 8 bits at the faster sample rates up to 16 bits at the lower rates. Low-power capability. Allows the use of "digital error correction" and “digital calibration” to greatly reduce the accuracy requirement of the internal flash ADCs and DACs respectively. Because each sample has to propagate through the entire pipeline before all its associated bits are available there is some data latency.

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**Pipeline ADC Digital correction Registers Stage1 Stage2 Stagek-1**

M bits Digital correction N1 bits N2 bits Nk-1 bits Nk bits Registers N1 bits N2 bits Nk-1 bits Nk bits Sample & hold Stage1 Stage2 Stagek-1 Stagek 2N + + k-1 Nk-1 bits - Residue amplifier Nk-1bit ADC Nk-1bit DAC

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**Pipeline ADC 8-bit (1.5-bit per stage )**

dout 8 bits Digital correction 2 bit 2 bit 2 bit 2 bits Φ1 Registers Φ2 2 bit 2 bit 2 bit 2 bits Sample & hold Stage1 Stage2 Stage6 Vin 1.5 bit ADC Anti-aliased signal Φ1 Φ2 Φ1 Φ1 Φ2 Φ1 Φ2

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**1.5-bit Pipelined Stage Vin C2 Vr C1 + 2 Vin Residue - Vin 1.5 bit DAC**

ADC + 2 Residue amplifier - 2 bits 1.5 bit ADC MDAC Vin Residue C1 C2 Φ2 Φ1 Vin 1/2Vref 4:1 MUX -1/2Vref X From ADC - + b0 b1 Vr Residue + - 1/4Vref -1/4Vref Vin Encoder 2 bits

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**Modeled as a Generic ADC with the specified reference levels**

1.5-bit ADC 1.5 bit DAC ADC + 2 Residue amplifier - 2 bits 1.5 bit ADC + - 1/4Vref -1/4Vref Vin Encoder 2 bits Modeled as a Generic ADC with the specified reference levels -1/4Vref 1/4Vref 00 01 10 Vin Digital code

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**1.5-bit MDAC Vin Vres = Vin(C1+C2)/C1 + Vr Vin C2 Vr C1 + 2 - 1.5 bit**

ADC + 2 Residue amplifier - 2 bits MDAC Residue Vin C1 C2 Φ2 Φ1 Vin 1/2Vref 4:1 MUX -1/2Vref X From ADC - + b0 b1 Vr Residue -1/4Vref Vin Residue -Vref -1/2Vref 1/2Vref Vref Vres = Vin(C1+C2)/C1 + Vr

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**1.5-bit MDAC nonidealities**

Φ2 Φ1 Vin 1/2Vref 4:1 MUX -1/2Vref X From ADC - + Capacitors mismatch |H| Cp CL Thermal noise Vth ≈ kT/C1 (Opamp noise neglected) Finite DC gain A0 Finite GBW, Cp and CL Defective settling Linear Slewing Partial Slewing εg= C1+(C1+ C2+ Cp)/A0 Vres Time Ideal value

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**1.5-bit Stage model + Vin Vres VADC Thermal Noise 1.5bit MDAC**

Including mismatch Defective settling Vres VADC 1.5 bit GenericADC 2-bits Ideal Nonideal

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**Digital Correction + + + + + + + Φ2 Φ1 b[7] b[6] b[5] b[4] b[3] b[2]**

sum + sum + sum + sum + sum + sum + sum Overflow cout cin cout cin cout cin cout cin cout cin cout cin cout cin a b a b a b a b a b a b a b Register Register Register Register Register Register s1[1] s1[0] Register Register Register Register Register s2[1] s2[0] Register Register Register Register s3[1] s3[0] Register Register Register s4[1] s4[0] Register Register Φ2 Φ1 s5[1] s5[0] Register s6[1] s6[0] s7[1] s7[0] sk[1] sk[0] are the bits from stage k

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**Pipelined 8-bit ADC model (Cadence)**

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**Pipelined 8-bit ADC simulation results**

PSD plot for 8-bit Pipelined ADC with 0 dB input signal Input frequency of 1.01MHz, Samples = 8192, Bandwidth = 5MHz 7.8 7.2 ENOB 61.778 54.427 SFDR (dB) THD (dB) 49.238 49.573 SNR (dB) 48.577 44.922 SNDR (dB)

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**Agenda ΣΔ ADC Conclusions Future Work Acknowledgements References**

1.5 bit MDAC Digital Correction Simulation results ΣΔ ADC ΣΔ Modulator SC integrator analysis Model Conclusions Future Work Acknowledgements References

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ΣΔ ADC Makes use of oversampling and ΣΔ modulation techniques to achieve high resolution. Used for low bandwidth and high-resolution applications but recently there is great interest for medium to high bandwidth applications. Due oversampling the requirements of the anti-aliasing filter are reduced. Modulator Digital Filter yo[n] Analog Anti-alias filter fs y[n] x[n] xi(t) xb(t)

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**∫ ΣΔ Modulator (ΣΔM) ΣΔM is the major analog component of the ADC.**

Due to its mixed-signal nature, non-idealities largely affect the performance of the ADC, i.e. the integrator, DAC mismatch. Quatization noise is shaped outside the band of interest. Several architectures exists depending on the number of integrators and the quantizer levels. N-level Quantizer ∫ g1 g2 DAC Lth order contains L integrators Single or Multi-bit depending on the quantizer Frequency (Hz) Magnitude (dB) Signal Digital Filter Shaped Quantization Noise White

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**SC integrator transient model**

Single pole OTA model Defective settling due to the OTA finite DC gain, GBW and SR limitations. Possible settling scenarios: Linear |Vai| ≤ Io/gm Slewing |Vai| > Io/gm and t < to Partial Slewing |Vai| > Io/gm and t ≥ to OTA Ci Cr Cint Cp CL Cinxt Vi Vr Va Vo + - Φ1 Φ2 -gmVa go Co Va Vo +Io -Io Parameter Description Ci, Cr Sampling capacitors Cint Integrating capacitor Cp,Co Input and output parasitic capacitances Cinxt Next stage input capacitance gm OTA transconductance go OTA output conductance Io OTA max output current to slewing time Vai Initial voltage at Va Sampling Φ1 Integration Φ2 Va Time Ideal value settling error

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**Second-Order ΣΔΜ Model**

gX1 = Ci/Cint gX2 = Cr/Cint Vi Φ1 Ci Cint Φ1 Φ2 Φ2 Φ2 Φ1 Va Cinxt - Vo Φ1 OTA + switches for both phases Φ1 and Φ2 Vr Φ1 Cr Φ2 Cp OTA + CL Φ2 Φ2 Φ1 Thermal Noise Thermal Noise SC intg SC intg Vin Jitter + g11 ∫ g21 ∫ 5-level 3-bits Flash ADC + g12 g22 3-bits 0.1% mismatch DAC DAC ILA Decoder 4-bits 4-bits 4-bits

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**ΣΔΜ Simulation Results GSM mode**

*Second order sigma-delta modulator with -6 dB input signal Input frequency of 30kHz, OSR = 65, N = 65536, BW = 200kHz (GSM mode) VHDL-AMS dB Actual data dB 0.65% error *This work has been accepted as a lecture presentation at the IEEE MWCAS 2005 conference, August 7-10 Cincinnati, Ohio.

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**ΣΔΜ Simulation Results WCDMA mode**

Second order sigma-delta modulator with -6 dB input signal Input frequency of 300kHz, OSR = 12, N = 65536, BW = 200kHz (GSM mode) VHDL-AMS dB Actual data dB 7.7% error

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Conclusions Behavioral modeling is a viable solution for the complex modeling and simulation of mixed-signal circuits. Verilog-A AHDL is suitable for modeling and simulation of mixed-signal circuits providing modularity and flexibility. Accurate behavioral models are achieved via validation. Behavioral modeling can be used as part of a Top-Down design approach but an iterative procedure is needed in order to refine the models. Effective circuits modeling techniques involves deep analysis including noise sources.

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Future Work Include more ADCs architectures such as integrating, sub-range and inter-leaved. Add specific DAC architectures such as resistor-string, capacitive, ΣΔ, multiplying, algorithmic and current-steering. Explore current based techniques. Model some other effects in common blocks such as the comparator metastability. Validate some of the models with available or future designs.

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**Acknowledgments Dr. Umesh Patel Dr. Manuel Jimenez at UPR Mayaguez**

Bob Kasa Wesley Powell Ellen Kozireski George Schoppet Alex Dea Damon Bradley Aaron Dixon George Winkert Betsy Pugel

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References M. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA CONVERTERS FOR COMMUNICATIONS”, Kluwer Academic Publishers, 2002. A. Rodriguez-Vazquez, F. Medeiro and E. Janssens. “CMOS Telecom Data Converters”. Kluwer Academic Publishers, 2003. F. Medeiro, A. Perez-Verdu and A. Rodriguez-Vazquez. “TOP-DOWN ESIGN OF HIGH-PERFORMANCE SIGMA-DELTA MODULATORS”, Kluwer Academic Publishers, 1999. D. Fitzpatrick and I. Miller. “ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE”, Kluwer Academic Publishers, 1998. B. Razavi. “Principles of Data Conversion System Design”. IEEE Press, 1995. T. M. Hancock. S. M. Pernia and A. C. Zeeb. “A Digitally Corrected 1.5-Bit/Stage Low Power 80Ms/s 10-Bit Pipelined ADC”. University of Michigan EECS , December 2002. M. Anderson, K. Norling and J. Yuan. “On the Effects of Static Errors in a Pipelined A/D Converter”. SSoCC 2003. R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Maloberti, K. Einwich, C. Clauss, P Schwarz and G. Noessing. “From System Specifications To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications. Proc. of the 2002 Design, Automation and Test in Europe, 2002. N. Mohan. “Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A“, .

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References J. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA CONVERTERS” PhD Dissertation, University of Nevada Las Vegas , May 2000. K. Kundert. “Top-Down Design of Mixed-Signal Circuits”. Cadence Design Systems, San Jose, California, 2000. K. W. Current, J. F. Parker, and W. J. Hardaker, “On Behavioral Modeling of Analog and Mixed-Signal Circuits”. IEEE Conference Record of the Twenty-Eighth Asilomar on Signals, Systems and Computers, vol. 1, pp264 – 268, 1994 F. O. Fernandez “Behavioral Modeling of ΣΔ Modulators”. Master’s Thesis University of Puerto Rico. Mayaguez, Puerto Rico 2003. T. Kugelstadt. “The operation of the SAR-ADC based on charge redistribution” TI Analog Applications Journal, Texas Instruments, 2000. J. Compiet, R de Jong, P, Wambacq, G, Vandersteen, S. Donnay, M. Engels and I. Bolsens. “HIGH-LEVEL MODELING OF A HIGH-SPEED FLASH A/D CONVERTER FOR MIXED-SIGNAL SIMULATIONS OF DIGITAL TELECOMMUNICATION FRONT-ENDS”. IEEE SSMSD, pp. 135 – 140, 2000. B. Brannon. “Aperture Uncertainty and ADC System Performance”. Analog Devices APPLICATION NOTE AN-501. “Understanding SAR ADCs”. Maxim-IC Application Note 387: Mar 01, 2001. “Understanding Pipelined ADCs”. Maxim-IC Application Note 383: Mar 01, 2001. “Understanding Flash ADCs”. Maxim-IC Application Note 810: Oct 02, 2001

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**printf (“Questions?“);**

#include <stdio.h> int main () { char str [100]; printf (“Questions?“); scanf ("%s",str); return 0; }

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**Acronyms ADC – Analog-to-digital converter**

AHDL – Analog Hardware Description Language DAC – Digital-to-analog converter DEM – Dynamic Element Matching ENOB – Effective number of bits. FS – Full scale voltage GBW – Gain bandwidth ILA – Individual Level Averaging INL – Integral non-linearity MDAC – Multiplying DAC SAR – Successive Approximation Register SFDR - Spurious Free Dynamic Range SNDR – Signal-to-noise plus distortion ratio SNR – Signal-to-noise ratio THD – Total Harmonic Distortion ΣΔΜ – Sigma-Delta Modulator

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