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Behavioral Modeling of Data Converters using Verilog-A George Suárez Graduate Student Electrical and Computer Engineering University of Puerto Rico, Mayaguez Code 564: Microelectronics and Signal Processing Branch NASA Goddard Space Flight Center

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1 Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Introduction Verilog-A Objectives Sample and Hold Analysis Jitter Noise Thermal noise Model Simulation results Generic DAC Analysis and model Dynamic element matching Simulation results

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2 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR ADC Analysis and model Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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3 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda 1.5 bit MDAC Digital Correction Simulation results qΣΔ ADC ΣΔ Modulator -SC integrator analysis -Model -Simulation results Conclusions Future Work Acknowledgements References

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4 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Introduction Transistor-level modeling and simulation is the most accurate approach for mixed-signal circuits. It becomes impractical for complex systems due to the long computational time required. Cell View No. of Transistors No. of Equations Simulation Time Transistor Level s ks 1 day, 10 hours, 42 min. Taken form the article: Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A Nitin Mohan, Sirific Wireless

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5 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Introduction This situation has led circuit designers to consider alternate modeling techniques: In addition, behavioral modeling can be effectively used in a top-down design approach. ApproachAccuracySpeedFlexibility Device models Custom C++ models Finite-difference equations Circuit-based macromodels Time-domain macromodels Behavioral models Cell View No. of Transistors No. of Equations Simulation Time Transistor Level s Behavioral s Transistor Level ks 1 day, 10 hours, 42 min. Behavioral s Efficient Testing of Analog/Mixed- Signal ICs using Verilog-A, Nitin Mohan, Sirific Wireless

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6 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Introduction Loop filter F(s) Phase comparator VCO A=1 fofo System Level (Matlab, C++, SystemC, AHDLs, etc…) Functional Level (SPICE, AHDLs) Transistor Level (SPICE) Layout Top-Down Design Approach Behavioral models + - V out V in A=1 + - V + V -

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7 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Verilog-A The Verilog-A is a high-level language developed to describe the structure and behavior of analog systems and their components. It is an extension to the IEEE 1364 Verilog HDL specification for digital design. The analog systems are described in Verilog-A in a modular way using hierarchy and different levels of modeling complexity. The motivation is to invest in a new higher level of abstraction in analog design and its combination with the digital one. `include "constants.vams" `include "disciplines.vams" module COMP (vin, vref, vout); output vout; electrical vout; input vin; electrical vin; input vref; electrical vref; parameter real slope = 100.0; parameter real offset = 0.0 ; vin vref vout

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8 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Objectives Build a set of analog and mixed-signal behavioral models using the Verilog-A AHDL, that allows a high level simulation of ADCs. Simulate some popular ADCs architectures such as: Flash ADC SAR ADC Pipelined ADC Simulate other common used mixed-signal circuits such as: ΣΔ Modulator Sample and Hold q Provide a general modeling approach for noise sources and other non-idealities. q Provide performance results for the simulated data converters such as spectrum measures SNR, SNDR, THD etc.

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9 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Introduction Verilog-A Objectives Sample and Hold Analysis Jitter Noise Thermal noise Model Simulation results Generic DAC Analysis and model Dynamic element matching Simulation results

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10 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Sample and Hold Finite DC gain A 0 Finite GBW C p and C L Defective settling Linear Slewing Partial Slewing R on 1 – exp[-t / (2R on C s )] Φs1Φs1 Jitter δ x(t+ δ) - x(t) ≈ δ x(t) Thermal noise V th ≈ kT/C s (Opamp noise neglected) ε g = 1 - C s /[ C s + (C s + C p )/A 0 ] CpCp CLCL + - V in V out CsCs Φs1Φs1 Time Ideal value |H||H| f Φs1Φs1

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11 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Clock jitter is due to the non-uniform sampling of the input signal. The magnitude of this error is a function of the statistical properties of the jitter and the input signal to the system. In sampled data systems, when a sinusoidal input is taken, the error introduced by jitter can be modeled by, Jitter Noise x(t+δ) - x(t) ≈ 2πf in δAcos(2πf in nt) ≈ δ x(t) δ where δ is the sampling uncertainty, this is taken to be a Gaussian random process with standard deviation Δt. ΔVΔV

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12 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Jitter Noise It is assumed that is a Gaussian random process with zero mean and standard deviation Δt. ΔtΔt -Δt Statistical properties of the jitter Input signal to the system

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13 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Thermal Noise Thermal noise in circuits is because of the random fluctuation of carriers due to thermal energy. Proportional to the temperature. It is assumed to be a Gaussian random process with zero mean.

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14 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Sample and Hold model Ideal S&H + Jitter Defective settling V out Ideal Nonideal Thermal Noise V in τ = R on C s Filter

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15 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Sample and Hold simulation results PSD for sampled signal of 0 dB, f in = MHz N = 8192, BW = 25MHz Increase in noise floor due nonidealities

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16 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Introduction Verilog-A Objectives Sample and Hold Analysis Jitter Noise Thermal noise Model Simulation results Generic DAC Analysis and model Dynamic element matching Simulation results

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17 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Generic DAC Mismatch in DAC units. INL Gain error Offset Mismatch in capacitors! (trimming can reduced it to 0.1% Increase in harmonics content) unit … V out + Generic DAC model including mismatch in units 2 B B -2 Thermometer decoder B bits

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18 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Integral non-linearityINL Quantization stepq Gain errorεgεg Full scale voltageFS Offset errorε off nominal gaing α(w a + off)yaya 1/(1+q ε g ) α (2 N-1 -1)qA FS/(2 N -1)q (1- ε 0 )x a + x a 3 ε 0 /A 2 wawa (INL)sqrt(27)/(2 N -2)ε0ε0 (l 1 ε g -ε off )qoffset -FS/(2g)l1l1 Generic DAC model DAC with mismatch + N bits α offset xaxa wawa vava v adc Digital input code Analog output INL = 0.5LSBGain error = 0.5LSB Ideal Nonideal Offset error = 0.5LSB

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19 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Dynamic Element Matching (DEM) techniques are used to minimize the effect of DAC units mismatch. DAC DEM techniques can be divided in deterministic and stochastic. Due to design complexity and non-scalability for modeling purposes it is easier to implement a general stochastic approach using randomization. DEM Improve the DAC performance by locating the distortion caused by the component mismatch errors in certain frequency bands. Magnitude (dB) f (Hz) Magnitude (dB) Spread the mismatch error energy across the spectrum generating white or colored noise in the DAC output. Magnitude (dB) f (Hz) Magnitude (dB)

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20 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez DAC 0.1% mismatch DEM off DEM on DEM simulation results By randomizing the DAC units (i.e. using a digital circuitry FSM with a system clock) the effect of the mismatch in the spectrum is reduced by reducing the harmonic distortion. In Verilog-A its rather simple to randomize uniformly the units. Assuming we have a system clock, for each rising edge of the clock signal we randomize the units. if(DEM_enable) begin generate i(1,`DAC_UNITS) begin temp = $dist_uniform(seed, 1, `DAC_UNITS); if(temp - floor(temp) >= 0.5) DEM[i] = ceil(temp); else DEM[i] = floor(temp); end end // Then select units stored in the array DEM[ ] for conversion unit … V out + 2 B B -2 Thermometer decoder B bits … Randomize …

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21 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR ADC Analysis and model Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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22 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Generic ADC model Analog input Digital output code INL = 0.5LSBGain error = 0.5LSB Ideal Nonideal Offset error = 0.5LSB Integral non-linearityINL Quantization stepq Gain errorεgεg Full scale voltageFS Offset errorε off nominal gaing α(w a + off) yaya 1/(1+qε g )α (2 N-1 -1)qA FS/(2 N -1)q (1- ε 0 )x a + x a 3 ε 0 /A 2 wawa (INL)sqrt(27)/(2 N -2)ε0ε0 (l 1 ε g -ε off )qoffset -FS/(2g) + q/2l1l1 Ideal ADC + N bits α offset xaxa wawa vava v adc

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23 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Generic ADC simulation results gain error =0.5LSB, offset error = 0.5LSB and INL = 0.5LSB SNDR = dB SNR = dB THD = dB SFDR = dB ENOB = 8 bits PSD plot for 8-bit generic ADC with 0 dB input signal f in of KHz, Samples = 8192, BW = 2MHz SNDR = dB SNR = dB THD = dB SFDR = dB ENOB = 7.7 bits

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24 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR ADC Analysis and model Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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25 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Flash ADC ……… +V ref -V ref R R R R R R … Decoder N bits Are made by cascading high- speed comparators. Are the fastest way to convert an analog signal to a digital signal. Ideal for applications requiring very large bandwidth. Typically consume more power than other ADC architectures and are generally limited to 8-bits resolution.

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26 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Flash ADC non-idealities OPAMP Finite DC gain Finite GBW Input resistance Output resistance Bias current Offset voltage Slew Rate Bubbles It is due the metastability of the comparators. (Future work will try model this effect) CcCc V + V - Vdd I bias CLCL GBW = g m1 /C C I5I5 I 5 = SR*C c Cadence provides a well accepted behavioral model of an non-ideal OPAMP/OTA for the most used AHDLs (Verilog-A, Verilog-AMS and VHDL-AMS)!

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27 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Flash ADC simulation results SNDR (dB) SNR (dB) THD (dB) SFDR (dB) ENOB Ideal Nonideal PSD plot for 8-bit Flash ADC with 0 dB input signal f in of 3.01MHz, Samples = 4096, BW = 5MHz

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28 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR ADC Analysis and model Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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29 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez SAR ADC Successive-approximation-register (SAR) ADCs) used for medium-to-high-resolution (8 to 16 bits) applications with sample rates under 5 Msps. Used in portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition. Provide low power consumption. An N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete.

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30 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez SAR ADC V DAC time Vin bit 3=0bit 2=1bit 1=0bit 0=1 ¼ Vref ½ Vref ¾ Vref Vref (MSB)(LSB) Successive Approximation Register (SAR) DAC Timing control Sample & hold Register Start CLK EOC N bits Vin + - Start CLK CONV SAH EOC CONV SAH Conversion time Anti-aliased signal

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31 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez 8.0ENOB SFDR (dB) THD (dB) SNR (dB) SNDR (dB) Ideal PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of KHz, Samples = 8192, Bandwidth = 250KHz SAR 8-bit ADC simulation results

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32 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Ideal SNDR 6.02N+1.76=49.92 dB PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of KHz, Samples = 8192, Bandwidth = 250KHz Increase in harmonics due mismatch in DAC units SAR 8-bit ADC simulation results

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33 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Ideal SNDR 6.02N+1.76=49.92 dB ENOB SFDR (dB) THD (dB) SNR (dB) SNDR (dB) PSD plot for 8-bit SAR ADC with 0 dB input signal Input frequency of KHz, Samples = 8192, Bandwidth = 250KHz Increase in harmonics due mismatch in DAC units SAR 8-bit ADC simulation results

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34 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda Generic ADC Analysis and model Simulation results Flash ADC Analysis and model Simulation results SAR ADC Analysis and model Simulation Results Pipelined ADC Analysis 1.5 bit Stage 1.5 bit ADC

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35 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda 1.5 bit MDAC Digital Correction Simulation results qΣΔ ADC ΣΔ Modulator -SC integrator analysis -Model -Simulation results Conclusions Future Work Acknowledgements References

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36 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Pipelined ADC Has become the most popular ADC architecture for sampling rates from a few MS/s up to 100MS/s, with resolutions from 8 bits at the faster sample rates up to 16 bits at the lower rates. Low-power capability. Allows the use of "digital error correction" and “digital calibration” to greatly reduce the accuracy requirement of the internal flash ADCs and DACs respectively. Because each sample has to propagate through the entire pipeline before all its associated bits are available there is some data latency.

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37 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Pipeline ADC Stage 1 Stage 2 Stage k-1 Stage k Registers Digital correction N 1 bitsN 2 bits N k-1 bits N k bits N 1 bitsN 2 bits N k-1 bits N k bits M bits Sample & hold N k-1 bit DAC N k-1 bit ADC + 2N2N k-1 Residue amplifier + - N k-1 bits

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38 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Pipeline ADC 8-bit (1.5-bit per stage ) Stage 1 Stage 2 Stage 6 Registers Digital correction 2 bit 2 bits 2 bit 2 bits 8 bits Sample & hold 1.5 bit ADC V in d out Φ1Φ1 Φ2Φ2 Φ2Φ2 Φ1Φ1 Φ2Φ2 Φ1Φ1 Φ1Φ1 Φ1Φ1 Φ2Φ2 Anti-aliased signal

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39 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez 1.5-bit Pipelined Stage MDAC1.5 bit ADC 1.5 bit DAC 1.5 bit ADC + 2 Residue amplifier bits /4V ref -1/4V ref V in Encoder 2 bits C1C1 C2C2 Φ2Φ2 Φ1Φ1 Φ1Φ1 Φ1Φ1 Φ2Φ2 V in 1/2V ref 4:1 MUX -1/2V ref 0 X From ADC Φ1Φ1 Φ2Φ2 - + b0b0 b1b1 VrVr Residue V in Residue

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40 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez 1.5 bit ADC 1.5-bit ADC 1.5 bit DAC 1.5 bit ADC + 2 Residue amplifier bits /4V ref -1/4V ref V in Encoder 2 bits Modeled as a Generic ADC with the specified reference levels -1/4V ref 1/4V ref V in Digital code

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41 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez 1.5-bit MDAC -1/4V ref V in Residue -V ref -1/2V ref 0 1/2V ref V ref V res = V in (C 1 +C 2 )/C 1 + V r C1C1 C2C2 Φ2Φ2 Φ1Φ1 Φ1Φ1 Φ1Φ1 Φ2Φ2 V in 1/2V ref 4:1 MUX -1/2V ref 0 X From ADC Φ1Φ1 Φ2Φ2 - + b0b0 b1b1 VrVr Residue 1.5 bit DAC 1.5 bit ADC + 2 Residue amplifier bits MDAC Residue V in

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42 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez 1.5-bit MDAC nonidealities Finite DC gain A 0 Finite GBW, C p and C L Defective settling Linear Slewing Partial Slewing C1C1 C2C2 Φ2Φ2 Φ1Φ1 Φ1Φ1 Φ1Φ1 Φ2Φ2 V in 1/2V ref 4:1 MUX -1/2V ref 0 X From ADC Φ1Φ1 Φ2Φ2 - + CpCp CLCL ε g = C 1 +(C 1 + C 2 + C p )/A 0 |H||H| Thermal noise V th ≈ kT/C 1 (Opamp noise neglected) Capacitors mismatch V res Time Ideal value

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43 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez 1.5-bit Stage model Defective settling V res Ideal Nonideal 1.5bit MDAC Including mismatch + Thermal Noise V in V ADC 1.5 bit GenericADC 2-bits

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44 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Digital Correction Register Φ2Φ2 Φ1Φ ba c in c out sum b a c in c out b a c in c out b a c in c out b a c in c out b a c in c out b a c in c out sum Overflow s 7 [1]s 7 [0] s 6 [1]s 6 [0] s 5 [1]s 5 [0] s 4 [1]s 4 [0] s 3 [1]s 3 [0] s 2 [1]s 2 [0] s 1 [1]s 1 [0] b[7]b[6]b[5]b[4]b[3]b[2]b[1]b[0] s k [1] s k [0] are the bits from stage k

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45 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Pipelined 8-bit ADC model (Cadence)

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46 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Pipelined 8-bit ADC simulation results ENOB SFDR (dB) THD (dB) SNR (dB) SNDR (dB) PSD plot for 8-bit Pipelined ADC with 0 dB input signal Input frequency of 1.01MHz, Samples = 8192, Bandwidth = 5MHz

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47 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Agenda 1.5 bit MDAC Digital Correction Simulation results qΣΔ ADC ΣΔ Modulator -SC integrator analysis -Model -Simulation results Conclusions Future Work Acknowledgements References

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48 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez ΣΔ ADC Makes use of oversampling and ΣΔ modulation techniques to achieve high resolution. Used for low bandwidth and high-resolution applications but recently there is great interest for medium to high bandwidth applications. Due oversampling the requirements of the anti-aliasing filter are reduced. Modulator Digital Filter y o [n] AnalogDigital Anti-alias filter fsfs y[n] x[n]x i (t)x b (t)

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49 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez ΣΔM is the major analog component of the ADC. Due to its mixed-signal nature, non-idealities largely affect the performance of the ADC, i.e. the integrator, DAC mismatch. Quatization noise is shaped outside the band of interest. Several architectures exists depending on the number of integrators and the quantizer levels. ΣΔ Modulator (ΣΔM) N-level Quantizer ∫ g1g1 g2g2 DAC L th order contains L integrators Single or Multi-bit depending on the quantizer Frequency (Hz) Magnitude (dB) Signal Digital Filter Shaped Quantization Noise White Noise

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50 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez SC integrator transient model Single pole OTA model Defective settling due to the OTA finite DC gain, GBW and SR limitations. Possible settling scenarios: Linear |V ai | ≤ I o /g m Slewing |V ai | > I o /g m and t < t o Partial Slewing |V ai | > I o /g m and t ≥ t o Sampling Φ 1 Integration Φ 2 VaVa Time Ideal value settling error -g m V a gogo CoCo VaVa VoVo +I o -I o ParameterDescription Ci, CrCi, Cr Sampling capacitors C int Integrating capacitor C p,C o Input and output parasitic capacitances C inxt Next stage input capacitance gmgm OTA transconductance gogo OTA output conductance IoIo OTA max output current toto slewing time V ai Initial voltage at V a

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51 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez VaVa Second-Order ΣΔΜ Model ∫ g 11 g 12 ∫ g 21 g 22 5-level 3-bits Flash ADC Decoder DAC 3-bits 4-bits + Thermal Noise + Thermal Noise Jitter SC intg OTA + switches for both phases Φ 1 and Φ 2 0.1% mismatch SC intg g X1 = C i /C int g X2 = C r /C int OTA CiCi CrCr C int CpCp CLCL C inxt ViVi VrVr VoVo + - Φ1Φ1 Φ2Φ2 Φ1Φ1 Φ2Φ2 Φ2Φ2 Φ1Φ1 Φ2Φ2 Φ1Φ1 Φ1Φ1 Φ2Φ2 Φ1Φ1 Φ2Φ2 V in DAC ILA 4-bits

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52 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez ΣΔΜ Simulation Results GSM mode VHDL-AMS dB Actual data dB *Second order sigma-delta modulator with -6 dB input signal Input frequency of 30kHz, OSR = 65, N = 65536, BW = 200kHz (GSM mode) *This work has been accepted as a lecture presentation at the IEEE MWCAS 2005 conference, August 7-10 Cincinnati, Ohio. 0.65% error

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53 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez ΣΔΜ Simulation Results WCDMA mode VHDL-AMS dB Actual data dB Second order sigma-delta modulator with -6 dB input signal Input frequency of 300kHz, OSR = 12, N = 65536, BW = 200kHz (GSM mode) 7.7% error

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54 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Conclusions Behavioral modeling is a viable solution for the complex modeling and simulation of mixed-signal circuits. Verilog-A AHDL is suitable for modeling and simulation of mixed-signal circuits providing modularity and flexibility. Accurate behavioral models are achieved via validation. Behavioral modeling can be used as part of a Top-Down design approach but an iterative procedure is needed in order to refine the models. Effective circuits modeling techniques involves deep analysis including noise sources.

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55 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Future Work Include more ADCs architectures such as integrating, sub- range and inter-leaved. Add specific DAC architectures such as resistor-string, capacitive, ΣΔ, multiplying, algorithmic and current-steering. Explore current based techniques. Model some other effects in common blocks such as the comparator metastability. Validate some of the models with available or future designs.

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56 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Acknowledgments Dr. Umesh Patel Dr. Manuel Jimenez at UPR Mayaguez Bob Kasa Wesley Powell Ellen Kozireski George Schoppet Alex Dea Damon Bradley Aaron Dixon George Winkert Betsy Pugel

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57 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez References M. Gustavsson, J. J. Wikner and N. N. Tan. “CMOS DATA CONVERTERS FOR COMMUNICATIONS”, Kluwer Academic Publishers, A. Rodriguez-Vazquez, F. Medeiro and E. Janssens. “CMOS Telecom Data Converters”. Kluwer Academic Publishers, F. Medeiro, A. Perez-Verdu and A. Rodriguez-Vazquez. “TOP-DOWN ESIGN OF HIGH-PERFORMANCE SIGMA-DELTA MODULATORS”, Kluwer Academic Publishers, D. Fitzpatrick and I. Miller. “ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE”, Kluwer Academic Publishers, B. Razavi. “Principles of Data Conversion System Design”. IEEE Press, T. M. Hancock. S. M. Pernia and A. C. Zeeb. “A Digitally Corrected 1.5-Bit/Stage Low Power 80Ms/s 10-Bit Pipelined ADC”. University of Michigan EECS , December M. Anderson, K. Norling and J. Yuan. “On the Effects of Static Errors in a Pipelined A/D Converter”. SSoCC R. Sommer, I. Rugen-Herzig, E. Hennig, U. Gatti, P. Malcovati, F. Maloberti, K. Einwich, C. Clauss, P Schwarz and G. Noessing. “From System Specifications To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications. Proc. of the 2002 Design, Automation and Test in Europe, N. Mohan. “Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A“,

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58 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez References J. W. Bruce II. “DYNAMIC ELEMENT MATCHING TECHNIQUES FOR DATA CONVERTERS” PhD Dissertation, University of Nevada Las Vegas, May K. Kundert. “Top-Down Design of Mixed-Signal Circuits”. Cadence Design Systems, San Jose, California, K. W. Current, J. F. Parker, and W. J. Hardaker, “On Behavioral Modeling of Analog and Mixed-Signal Circuits”. IEEE Conference Record of the Twenty-Eighth Asilomar on Signals, Systems and Computers, vol. 1, pp264 – 268, 1994 F. O. Fernandez “Behavioral Modeling of ΣΔ Modulators”. Master’s Thesis University of Puerto Rico. Mayaguez, Puerto Rico T. Kugelstadt. “The operation of the SAR-ADC based on charge redistribution” TI Analog Applications Journal, Texas Instruments, J. Compiet, R de Jong, P, Wambacq, G, Vandersteen, S. Donnay, M. Engels and I. Bolsens. “HIGH-LEVEL MODELING OF A HIGH-SPEED FLASH A/D CONVERTER FOR MIXED-SIGNAL SIMULATIONS OF DIGITAL TELECOMMUNICATION FRONT-ENDS”. IEEE SSMSD, pp. 135 – 140, B. Brannon. “Aperture Uncertainty and ADC System Performance”. Analog Devices APPLICATION NOTE AN-501. “Understanding SAR ADCs”. Maxim-IC Application Note 387: Mar 01, “Understanding Pipelined ADCs”. Maxim-IC Application Note 383: Mar 01, “Understanding Flash ADCs”. Maxim-IC Application Note 810: Oct 02, 2001

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59 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez printf (“Questions?“); #include

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60 NASA Goddard Space Flight Center Code 564 Microelectronic and Signal Processing Behavioral Modeling of ADCs using Verilog-A by George Suárez Acronyms ADC – Analog-to-digital converter AHDL – Analog Hardware Description Language DAC – Digital-to-analog converter DEM – Dynamic Element Matching ENOB – Effective number of bits. FS – Full scale voltage GBW – Gain bandwidth ILA – Individual Level Averaging INL – Integral non-linearity MDAC – Multiplying DAC SAR – Successive Approximation Register SFDR - Spurious Free Dynamic Range SNDR – Signal-to-noise plus distortion ratio SNR – Signal-to-noise ratio THD – Total Harmonic Distortion ΣΔΜ – Sigma-Delta Modulator

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