Presentation is loading. Please wait.

Presentation is loading. Please wait.

ELEN 468 Lecture 61 ELEN 468 Advanced Logic Design Lecture 6 Delay Models.

Similar presentations


Presentation on theme: "ELEN 468 Lecture 61 ELEN 468 Advanced Logic Design Lecture 6 Delay Models."— Presentation transcript:

1 ELEN 468 Lecture 61 ELEN 468 Advanced Logic Design Lecture 6 Delay Models

2 ELEN 468 Lecture 62 Delay Models

3 ELEN 468 Lecture 63 Propagation Delay Xin Xout Tpd_1_0 Xin Xout t t 50%Vdd

4 ELEN 468 Lecture 64 Delay Models Gate delay Intrinsic delay Layout-induced delay due to capacitive load Waveform slope-induced delay Net delay/transport delay Signal propagation delay along interconnect wires Module path delay Delay between input port and output port

5 ELEN 468 Lecture 65 Signal Transitions Rising 0->1, x->1, z->1 Falling 1->0, x->0, z->0 Turnoff 0->z, 1->z, x->z

6 ELEN 468 Lecture 66 Model Delay Uncertainties: Min, Typical and Max Delays Process variations Defects, etching errors, photomask misalignment … Power-ground noise Power supply level lower than ideal level Ground voltage level greater than zero Crosstalk noise Signal switching in neighboring wires causes extra net delay

7 ELEN 468 Lecture 67 Gate Delay and (yout, x1, x2);// default, zero gate delay and #3 (yout, x1, x2);// 3 units delay for all transitions and #(2,3) G1(yout, x1, x2); // rising, falling delay and #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4); // Multiple instances a_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoff bufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable); // min:typ:max / rise, fall, turnoff and (yout, x1, x2);// default, zero gate delay and #3 (yout, x1, x2);// 3 units delay for all transitions and #(2,3) G1(yout, x1, x2); // rising, falling delay and #(2,3) G1(yout, x1, x2), G2(yout2, x3, x4); // Multiple instances a_buffer #(3,5,2) (yout, x); // UDP, rise, fall, turnoff bufif1 #(3:4:5, 6:7:9, 5:7:8) (yout, xin, enable); // min:typ:max / rise, fall, turnoff Simulators simulate with only one of min, typ and max delay values Selection is made through compiler directives or user interfaces Default delay is typ delay

8 ELEN 468 Lecture 68 Options for Delay Specifications dr = rising delay, df = falling delay, dz = turnoff delay If 2 delays are specified d* = d** = min ( dr, df ) If 3 delays are specified d* = min( dr, df, dz ), d** = dz Logic value before transition Logic value after transition 01xz 0drd*dz 1dfd*dz xdfdrd** zdfdrd*

9 ELEN 468 Lecture 69 Time Scales Time scale directive: ‘ timescale / time_unit -> physical unit of measure, time scale of delay time_precision -> time resolution/minimum step size during simulation time_unit  time_precision Unit/precisionDelay specification Simulator time step Delay value in simulation 1ns / 100ps#40.1ns4.0ns 100ns / ns#41ns400ns 10ns / 100ps# ns46.3ns

10 ELEN 468 Lecture 610 Example of Time Scale `timescale 1 ns / 10 ps module modA( y, x1, x2 ); input x1, x2; output y; nand #(3.225, 4.237) ( y, x1, x2 ); endmodule `timescale 10 ns / 10 ns module modB(); reg x1, x2; wire y; modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin #5 x1 = 0; x2 = 0; #5 x2 = 1; #5 x1 = 1; #5 x2 = 0; end endmodule

11 ELEN 468 Lecture 611 Example of Time Scale `timescale 1 ns / 10 ps module modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2 ); endmodule `timescale 10 ns / 10 ns module modB(); … … modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin #5 x1 = 0; x2 = 0; #5 x2 = 1; #5 x1 = 1; #5 x2 = 0; end endmodule `timescale 1 ns / 10 ps module modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2 ); endmodule `timescale 10 ns / 10 ns module modB(); … … modA M1(y, x1, x2); initial begin $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin #5 x1 = 0; x2 = 0; #5 x2 = 1; #5 x1 = 1; #5 x2 = 0; end endmodule $t$real_tx1x2y x1=xx2=xy=x x1=0x2=0y=x x1=0x2=0y= x1=0x2=1y= x1=1x2=1y= x1=1x2=1y= x1=1x2=0y= x1=1x2=0y=1

12 ELEN 468 Lecture 612 Time Display Format `timescale 1 ns / 1 ps module modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2 ); endmodule `timescale 10 ns / 10 ns module modB(); … … modA M1(y, x1, x2); initial begin $timeformat (-12, 1, “ ps”, 10); $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin #5 x1 = 0; x2 = 0; #5 x2 = 1; #5 x1 = 1; #5 x2 = 0; end endmodule `timescale 1 ns / 1 ps module modA( y, x1, x2 ); … … nand #(3.225, 4.237) ( y, x1, x2 ); endmodule `timescale 10 ns / 10 ns module modB(); … … modA M1(y, x1, x2); initial begin $timeformat (-12, 1, “ ps”, 10); $monitor ( $time, “%f x1= %b x2= %b y= %b”, $realtime, x1, x2, y ); end initial begin #5 x1 = 0; x2 = 0; #5 x2 = 1; #5 x1 = 1; #5 x2 = 0; end endmodule $t $real_t x1x2y ps x1=xx2=xy=x ps x1=0x2=0y=x ps x1=0x2=0y= ps x1=0x2=1y= ps x1=1x2=1y= ps x1=1x2=1y= ps x1=1x2=0y= ps x1=1x2=0y=1 $timeformat ( units_number, precision_number, suffix_string, min_field_width );

13 ELEN 468 Lecture 613 Unit Number in Time Format Unit_numberTime unitUnit_numberTime unit 01s-810ns 100ms-91ns -210ms-10100ps -31ms-1110ps -4100us-121ps -510us-13100fs -61us-1410fs -7100ns-151fs

14 ELEN 468 Lecture 614 Net Delay … wire #2 y_tran; and #3 (y_tran, x1, x2); buf #1 (buf_out, y_tran); and #3 (y_inertial, x1, x2); … wire #2 y_tran; and #3 (y_tran, x1, x2); buf #1 (buf_out, y_tran); and #3 (y_inertial, x1, x2); … x1 x2 y_tran y_inertial buf_out x1 x2 y_inertial y_tran buf_out

15 ELEN 468 Lecture 615 Examples of Net Delay module xor1( y, a, b ); inputa, b; outputy; parameterdelay = 5; assign #delay y = a ^ b; endmodule module xor1( y, a, b ); inputa, b; outputy; parameterdelay = 5; assign #delay y = a ^ b; endmodule module xor2( y, a, b ); inputa, b; outputy; wire#5 y; assign y = a ^ b; endmodule module xor2( y, a, b ); inputa, b; outputy; wire#5 y; assign y = a ^ b; endmodule module xor3( y, a, b ); inputa, b; outputy; parameter wire_delay = 5; parameter gate_delay =3; wire #wire_delay y; assign #gate_delay y = a ^ b; endmodule module xor3( y, a, b ); inputa, b; outputy; parameter wire_delay = 5; parameter gate_delay =3; wire #wire_delay y; assign #gate_delay y = a ^ b; endmodule

16 ELEN 468 Lecture 616 Module Delays and Paths In structural description, module delays can be obtained by tracing gate and net delays In behavioral description, module paths can be described separately to allow delay descriptions

17 ELEN 468 Lecture 617 Module Paths Simple module paths Unconditional direct input to output path State-dependent paths Exists when certain condition is satisfied Describe transparent latch Edge-dependent paths Exists for a synchronizing signal Describe edge-triggered flip-flop

18 ELEN 468 Lecture 618 Simple Module Path Source of path must be a net declared as input or output Destination of path must be a net or reg declared as output or inout Parallel paths, “=>” Full connection paths, “*>”

19 ELEN 468 Lecture 619 Example of Simple Module Path Delay module nand1( out, A, B ); outputout; inputA, B; nand ( out, A, B ); specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 ); // 0->1, 1->0, 0->z, z->1, 1->z, z->0 endspecify endmodule module nand1( out, A, B ); outputout; inputA, B; nand ( out, A, B ); specify ( A,B *> out ) = ( 15, 14, 11, 10, 16,15 ); // 0->1, 1->0, 0->z, z->1, 1->z, z->0 endspecify endmodule A B out Specify blocks declare paths Its path can override structural delays

20 ELEN 468 Lecture 620 Edge-Sensitive Paths module edge_FF ( clock, data, clear, preset, q ); input clock, data, clear, preset; output q; specify specparam t_rise_clk_q = 100; t_fall_clk_q = 120; t_rise_ctl_q = 50; t_fall_ctl_q = 60; ( posedge clock *> (q:data) ) = ( t_rise_clk_q, t_fall_clk_q ); ( clear, preset *> q ) = ( t_rise_ctl_q, t_fall_ctl_q ); endspecify … endmodule module edge_FF ( clock, data, clear, preset, q ); input clock, data, clear, preset; output q; specify specparam t_rise_clk_q = 100; t_fall_clk_q = 120; t_rise_ctl_q = 50; t_fall_ctl_q = 60; ( posedge clock *> (q:data) ) = ( t_rise_clk_q, t_fall_clk_q ); ( clear, preset *> q ) = ( t_rise_ctl_q, t_fall_ctl_q ); endspecify … endmodule

21 ELEN 468 Lecture 621 State-Dependent Paths specify if ( enable ) ( data *> q ) = ( t_rise_clk_q, t_fall_clk_q ); endspecify specify if ( !set && !clear ) ( posedge clock *> ( q:data )) = ( t_rise_clk_q, t_fall_clk_q ); endspecify specify if ( enable ) ( data *> q ) = ( t_rise_clk_q, t_fall_clk_q ); endspecify specify if ( !set && !clear ) ( posedge clock *> ( q:data )) = ( t_rise_clk_q, t_fall_clk_q ); endspecify

22 ELEN 468 Lecture 622 Path Polarity ( siga +*> q1 ) = delay_to_q1;// positive path polarity ( sigb -*> q2 ) = delay_to_q2;// negative path polarity ( sigc *> q3 ) = delay_to_q3;// unknown polarity ( siga +*> q1 ) = delay_to_q1;// positive path polarity ( sigb -*> q2 ) = delay_to_q2;// negative path polarity ( sigc *> q3 ) = delay_to_q3;// unknown polarity Specify whether a transition at output of a path has the same direction (rising or falling) as the input

23 ELEN 468 Lecture 623 Specify Block Parameters module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); endspecify endmodule module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); endspecify endmodule Local to specify block

24 ELEN 468 Lecture 624 Specify Pulse Width module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); pathpulse$ ( : : ); endspecify endmodule module nand1 ( O, A, B ); input A, B; output O; nand ( O, A, B ); specify specparam T01 = 1.13:3.09:7.75; T10 = 0.93:2.50:7.34; ( A=>O ) = ( T01, T10 ); ( B=>O ) = ( T01, T10 ); pathpulse$ ( : : ); endspecify endmodule Specify inertial delays

25 ELEN 468 Lecture 625 Pulse Reject Limit and Error Limit specify ( clk => q ) = 10; ( data => q ) = 7; ( clr, preset *> q ) = 3; specparam pathpulse$ clk$q = ( 3, 8 ); pathpulse$ clr$q = ( 0, 5 ); pathpulse$ = 4; endspecify specify ( clk => q ) = 10; ( data => q ) = 7; ( clr, preset *> q ) = 3; specparam pathpulse$ clk$q = ( 3, 8 ); pathpulse$ clr$q = ( 0, 5 ); pathpulse$ = 4; endspecify Reject limit Error limit If pulse_width < reject_limit, pulse is rejected If reject_limit < pulse_width < error_limit, ‘x’ is at output If error_limit < pulse_width, signal is transported to output Single value for both reject and error For any other paths not specified


Download ppt "ELEN 468 Lecture 61 ELEN 468 Advanced Logic Design Lecture 6 Delay Models."

Similar presentations


Ads by Google