Presentation is loading. Please wait.

Presentation is loading. Please wait.

ECE 551 Digital Design And Synthesis Lecture 03 RTL Verilog Examples Intro to Behavioral Verilog.

Similar presentations


Presentation on theme: "ECE 551 Digital Design And Synthesis Lecture 03 RTL Verilog Examples Intro to Behavioral Verilog."— Presentation transcript:

1 ECE 551 Digital Design And Synthesis Lecture 03 RTL Verilog Examples Intro to Behavioral Verilog

2 Topics  RTL Verilog Examples  Commenting in Verilog  Introduction to Behavioral Verilog  Blocks and Triggers  Procedural Assignments  Edge Triggering 2

3 RTL Example – Dual Mux module mux2_32b (mux_out_1, mux_out_2, data_1, data_0, select); output [31: 0] mux_out_1, mux_out_2; input [31: 0] data_1, data_0; input select; assign mux_out_1 = select ? data_1 : data_0; assign mux_out_2 = select ? data_0 : data_1; endmodule  Can you describe what this module does?  Does the ordering of the assignments matter? 3

4 Example: Priority Encoder 4 module prienc_4to2( output [1:0] out, input in0, in1, in2, in3); endmodule Use the conditional operator and a single continuous assignment statement Give in3 highest priority.

5 Implicit Continuous Assignments  Can create an implicit continuous assign  Goes in the wire declaration wire [3:0] sum = a + b;  Can be a useful shortcut to make code succinct, but doesn’t allow fancy LHS combos assign {cout, sum} = a + b + cin;  Personal choice  You are welcome to use it when appropriate 5

6 Implicit Net Declarations  When wire is used but not declared, it is implied module majority(output out, input a, b, c); assign part1 = a & b; assign part2 = a & c; assign part3 = b & c; assign out = part1 | part2 | part3; endmodule  Implicit declaration is risky  Makes code difficult to follow (how many bits?)  Breaks compatibility with some documentation tools  Disable by using `default_nettype none directive  Helps to avoid wasting time on typos  You will need to explicitly declare input/output types!  Don’t use them in Homework 6

7 Propagation Delay 1 module AOI_4(y_out, x_in); input [4:1] x_in; output y_out; wire #1 y1 = x_in[1] & x_in[2]; // Bitwise and operations wire #1 y2 = x_in[3] & x_in[4]; // using implicit continuous assign. wire #1 y_out = ~ (y1 | y2); // Bitwise NOR operation endmodule  Are these inertial or transport delays?  Does the order of declarations matter? 7

8 Propagation Delay 2 module AOI_4(y_out, x_in); input [4:1] x_in; output y_out; wire y1, y2; assign #1 y1 = x_in[1] & x_in[2]; // Bitwise and operations assign #1 y2 = x_in[3] & x_in[4]; // using implicit continuous assign. assign #1 y_out = ~ (y1 | y2); // Bitwise NOR operation endmodule  Are these inertial or transport delays?  Does the order of declarations matter? 8

9 Latches  Continuous assignments with feedback module latch(output q_out, input data_in, enable); assign q_out = enable ? data_in : q_out; endmodule module latch_reset(output q_out, input data_in, enable, reset); assign q_out = reset ? 0 : (enable ? data_in : q_out); endmodule  How could we change these to be 8-bit latches?  How could we make the enable active low?  Does enable or reset have higher priority? 9

10 Latches  A lot of designers recommend that you avoid using latches in designs you intend to Synthesize Why do we avoid Latches?  The presence of latches can cause problems during the Static Timing Analysis phase of Synthesis  It is more difficult to get the timing behavior of latches to match simulation because they are sensitive to glitches  Some design platforms – like many FPGAs – do not support synthesis of latches. Use FFs instead of Latches! 10

11 Example: Rock-Paper-Scissors  module rps(output win, player, input [1:0] p0guess, p1guess);  Assumptions:  Input: p0guess, p1guess = {0 for rock, 1 for paper, 2 for scissors} – assume 3 will never happen  Output: player is 0 if p0 wins, 1 if p1 wins, and don’t care if there is a tie  Output: win is 0 if there is a tie and 1 if a player wins  Reminders  Paper covers rock, scissors cut paper, rock smashes scissors  Is a tie if guesses are the same 11

12 Example: Rock-Paper-Scissors  Two possible approaches  Figure out Boolean equations for win and player and implement these using continuous assignments  Use bitwise operators  Examine what the various items equal and do logical operations on these  Use equality and logical operators 12

13 Solution 1: Rock-Paper-Scissors module rps(win, player, p0guess, p1guess); input [1:0] p0guess, p1guess; output win, player; What steps do we need to find the Boolean representation?  Write a truth table  Create k-maps for each output  Write minterms/maxterms  Simplify Boolean expressions (optional) endmodule 13

14 Solution 1: Rock-Paper-Scissors module rps(win, player, p0guess, p1guess); input [1:0] p0guess, p1guess; output win, player; assign win = |(p0guess ^ p1guess); assign player = (p1guess[0] ^ p0guess[1]) | (p1guess[1] & p0guess[0]); endmodule What does this description synthesize to? 14

15 Solution 2: Rock-Paper-Scissors module rps(win, player, p0guess, p1guess); input [1:0] p0guess, p1guess; output win, player; How can we express this in terms of Relational and Equality operators? Rock = 2’d0, Paper = 2’d1, Scissors = 2’d2 endmodule 15

16 Example: FSM Pattern Detector 16 Recognize the occurrence of the bit pattern 111. The output is to be a 1 when the two previous inputs were 11 and the current input is 1. Use flip-flops dff_async_pc(input d, output q, input pre, clr, clk); pre (preset) and clr (clear) are asynchronous flip-flop inputs Draw a state diagram, then use a one-hot state assignment. module pattern111 (output y, input x, rst, clk); wire [2:0] cur; // current state (flip-flop outputs) wire [2:0] next; // next state (flip-flop inputs) //Flip-flop Instantiations // Input equations // Output equation endmodule

17 Example: FSM 17 Use flip-flops dff_async_pc(input d, output q, input pre, clr, clk); module pattern111 (output y, input x, rst, clk); wire [2:0] cur; // current state (flip-flop outputs) wire [2:0] next; // next state (flip-flop inputs) //Flip-flop Instantiations dff_async_pc // Input equations assign next[0] = assign next[1] = assign next[2] = // Output equation assign y = endmodule

18 Topics  RTL Verilog Examples  Commenting in Verilog  Introduction to Behavioral Verilog  Blocks and Triggers  Procedural Assignments  Edge Triggering 18

19 A Brief Comment on Comments  Make your code easier to understand  assign msg = addr & 16’h1FFF; //mask off sender ID  // this is a comment (to the end of the line)  Block comments are also supported, i.e. /* */  Make them useful!  Give an overview of what the module does  Label major sections of code (e.g., next state logic, output equations, flip-flops).  Comment the portions of the code that may be unclear  Don’t go overboard: wire [7:0] sum; //an 8-bit sum  Use them where needed in remaining assignments & project 19

20 Topics  RTL Verilog Examples  Commenting in Verilog  Introduction to Behavioral Verilog  Blocks and Triggers  Procedural Assignments  Edge Triggering 20

21 Behavioral Verilog  Instead of describing what the hardware looks like, describe what you want the hardware to do  Goal: Abstract away the details of the hardware implementation to make design easier  In reality: Mixed success  The synthesizer creates a hardware structure that does the same thing as your description  … but the synthesizer has to be able to realize your description using real hardware constraints  This is why not all Verilog constructs are supported 21

22 Behavioral Verilog  Use procedural blocks: initial, always  Blocks contain an ordered series of statements  Abstract – works *somewhat* like software  Be careful to still remember it’s hardware if you want to synthesize!  Parallel operation across blocks  All blocks in all modules operate simultaneously  Sequential or parallel operation within blocks  Depends on the way the block is written  Will discuss this in a later lecture  LHS of assignments must be variables (reg)  Not necessarily “registers” 22

23 Types of Blocks  initial  Behavioral block operates ONCE  Starts at time 0 (beginning of operation)  Useful for testbenches  Inappropriate for combinational logic  Usually cannot be synthesized  Can sometimes provide initialization of memories/FFs  Depends on the synthesizer  always  Behavioral block operates CONTINUOUSLY  Can use a sensitivity list to control operation; @(a, b, c) 23

24 initial vs. always 24 reg [7:0] v1, v2, v3, v4; initial begin v1 = 1; #2 v2 = v1 + 1; v3 = v2 + 1; #2 v4 = v3 + 1; v1 = v4 + 1; #2 v2 = v1 + 1; v3 = v2 + 1; end reg [7:0] v1, v2, v3, v4; always begin v1 = 1; #2 v2 = v1 + 1; v3 = v2 + 1; #2 v4 = v3 + 1; v1 = v4 + 1; #2 v2 = v1 + 1; v3 = v2 + 1; end  What values does each block produce?

25 initial Blocks 25 `timescale 1ns /1ns module t_full_adder; reg [3:0] stim; wire s, c; // instantiate UUT full_adder(sum, carry, stim[2], stim[1], stim[0]); // monitor statement is special - only needs to be made once, initial $monitor(“%t: s=%b c=%b stim=%b”, $time, s, c, stim[2:0]); // tell our simulation when to stop initial #50 $stop; initial begin // stimulus generation for (stim = 4’d0; stim < 4’d8; stim = stim + 1) begin #5; end endmodule all initial blocks start at time 0 single-statement block multi-statement block enclosed by begin and end

26 always Blocks  Operates continuously or on a trigger list  Can be used side-by-side with initial blocks  Cannot “nest” initial or always blocks  Useful example of continuous always block: reg clock; initial clock = 1’b0; always clock = #10 ~clock;  Clock generator goes in the testbench. This doesn’t synthesize. 26

27 always blocks with sensitivity lists  Conditionally behave as described by always block  Always blocks are continuously operating  If sensitivity list present, continuously checking triggers  Any change on sensitivity list, block is evaluated always @(a, b, c) begin … end  Sounds like software! It isn’t!  This is how the simulator treats it  Hardware effectively has the same resulting operation  Hardware doesn’t “wait to see” changes on trigger list  Just reacts to changes on the inputs  See examples in later slides to see what is actually created 27

28 Sensitivity Lists  Uses “event control operator” @  When net or variable in trigger list changes, always block is triggered 28 always @(in1, in0, sel) begin if (sel == 1’b0) out = in0; else out = in1; end always @(a, b, c) begin a1 = a & b; a2 = b & c; a3 = a & c; carry = a1 | a2 | a3; end always @(state, input) begin if (input == 1’b0) begin if (state != 2’b11) nextstate = state + 1; else nextstate = 2’b00; end else nextstate = state; end What goes in the sensitivity list for combinational logic?

29 Event or and *  Original (Verilog 95) way to specify trigger list always @ (X1 or X2 or X3)  In Verilog 2001 can use, instead of or always @ (X1, X2, X3)  Verilog 2001 also has * for combinational only always @ (*)  Shortcut that includes all nets/variables used on RHS in statements in the block  Also includes variable used in if statements; if (x)  In homework and on exams you may be asked to specify inputs to trigger list without *  i.e., be aware of the inputs to your hardware 29

30 Example: Comparator 30 module compare_4bit_behave(output reg A_lt_B, A_gt_B, A_eq_B, input [3:0] A, B);

31 Edge Triggering  A negedge is on the transitions  1  x, z, 0  x, z  0  A posedge is on the transitions  0  x, z, 1  x, z  1  Used for clocked (synchronous) logic always @ (posedge clk) register <= register_input; 31 Different assignment operator!

32 Example: Basic DFF 32 module dff(output reg q, input d, input clk); always @(posedge clk) begin q <= d; end endmodule Why is q of type reg?

33 Combinational vs. Sequential Blocks  Combinational  Not edge-triggered  All “inputs” (RHS nets/variables) are triggers  Does not depend on clock  Sequential  Edge-triggered by clock signal  Only clock (and possibly reset) appear in trigger list  Block can include combinational logic, but only as input to flip-flops/registers. Cannot have combinational outputs  Be careful when trying to mix combinational and sequential behavior in the same block. 33

34 Review Questions  What is the main difference between an initial block and an always block?  What is the difference between always@(a, b, c) and always@(a or b or c)  Write an always block that implements a 4-bit adder with input a[3:0], b[3:0], cin and outputs sum[3:0] and cout.  Fill in the sensitivity list for the following piece of combinational logic always @( ) if (x) z = a + b; else z = a – b;  Fill in the sensitivity list for the following piece of sequential logic always @() if (!reset) count <= 0; else count <= count+1; 34


Download ppt "ECE 551 Digital Design And Synthesis Lecture 03 RTL Verilog Examples Intro to Behavioral Verilog."

Similar presentations


Ads by Google