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Towards ideal codes: looking for new turbo code schemes Ph.D student: D. Kbaier Ben Ismail Supervisor: C. Douillard Co-supervisor: S. Kerouédan.

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Presentation on theme: "Towards ideal codes: looking for new turbo code schemes Ph.D student: D. Kbaier Ben Ismail Supervisor: C. Douillard Co-supervisor: S. Kerouédan."— Presentation transcript:

1 Towards ideal codes: looking for new turbo code schemes Ph.D student: D. Kbaier Ben Ismail Supervisor: C. Douillard Co-supervisor: S. Kerouédan

2 Electronics Department Ph.D defense, Monday 26 th September 2011page 1 What is a good code? Ideal system Limits to the correction capability of any code Established by Shannon Good convergence Error rate greatly decreases close to the theoretical limit Waterfall region High asymptotic gain Search for the ideal encoder/decoder pair Dilemma: good convergence versus high MHD

3 Electronics Department Ph.D defense, Monday 26 th September 2011page 2 Turbo codes

4 Electronics Department Ph.D defense, Monday 26 th September 2011page 3 Constraints on λ Extract from my Ph.D report:

5 Electronics Department Ph.D defense, Monday 26 th September 2011page 4 Choice of the post-encoder Influences performance in both the waterfall and error floor region Must be simple  low memory RSC codes The code is made tail biting  accumulator Must not exhibit too much error amplification EXIT analysis

6 Electronics Department Ph.D defense, Monday 26 th September 2011page 5 Choice of the post-encoder k = 1146 bits R = 2/3 λ = 1/4 MAP, 10 iterations

7 Electronics Department Ph.D defense, Monday 26 th September 2011page 6 Simulated performance of the 3D TC with random and regular interleavers Π’ Regular permutation: Achieves the maximum value of the spread Performs better than the random interleaver k = 762 bits λ = 1/8 k = 762 bits R = 1/2 λ = 1/8

8 Electronics Department Ph.D defense, Monday 26 th September 2011page 7 Performance of 3GPP2 based 3D TCs

9 Electronics Department Ph.D defense, Monday 26 th September 2011page 8 Relation between λ and d min Extract from my Ph.D report pages 38-39: The authors in [63, 64] analyzed the asymptotic weight distribution of 3D TCs and showed that their typical minimum distance may, depending on certain parameters, asymptotically grow linearly with the block length.

10 Electronics Department Ph.D defense, Monday 26 th September 2011page 9 Relation between λ and d min

11 Electronics Department Ph.D defense, Monday 26 th September 2011page 10 3D TCs hardware implementation issues: decoder architecture and complexity analysis 3D turbo decoder architecture: Input module -Double input buffer -Input buffer divided into as many MBs as P -Parallelism  different throughputs Decoder module -P SISO processors & an extrinsic memory -Performs I iterations on the frame stored in the input module -Writes the decoded codeword into the output module Output module -Stores the hard decisions produced by the decoder module -Sends them to the output of the decoder No parallelism is considered for the predecoder The predecoder has much less data to process than the main SISO decoders -Only λ = 1/4 or λ = 1/8 of the parity bits are reencoded

12 Electronics Department Ph.D defense, Monday 26 th September 2011page 11 Typical overall 3D turbo decoder architecture Decoded bits MB P-1 MB 0 MB 1 MB P-1 MB 0 Input module SISO P-1 SISO 1 SISO 0 Extrinsic memory (syste- matic) Main decoder module Input samples MB P-1 MB 0 MB 1 Output module Extrinsic memory (parity) PREDEC SISO Pre-decoder module MB 1

13 Electronics Department Ph.D defense, Monday 26 th September 2011page 12 Max-Log-MAP decoder complexity analysis Arithmetic and logical operations Branch metrics Forward and backward state metrics Soft and hard decisions Extrinsic information related to information bits Extrinsic LLRs related to redundancy bits

14 Electronics Department Ph.D defense, Monday 26 th September 2011page 13 Memory requirements for the 3D turbo decoder The amount of RAM and ROM memory TC permutation parameters  small amount of ROM memory For the RAM memory: 2 input buffers for each data sequence -Including systematic and parity bits -Stemming from the transmission channel RAM to store the extrinsics -Additional extrinsics for the 3D TC RAM to store the hardware decision at decoder output Inside the SISO decoding process, state metrics have to be stored at each iteration

15 Electronics Department Ph.D defense, Monday 26 th September 2011page 14 Optimization method

16 Electronics Department Ph.D defense, Monday 26 th September 2011page 15 Optimization results for k = 1530 data bits d η(d) Total increase in d min by + 42 %  a gain of 2.5 decades in the error floor k = 1530 R = 1/2 λ = 1/8 Max-Log-MAP, 10 iterations d202122… η(d) Before optimization After optimization

17 Electronics Department Ph.D defense, Monday 26 th September 2011page 16 Optimization results for k = 1146 data bits k = 1146 R = 2/3 λ = 1/4 Distance Multiplicity13≥1≥2 Address 1 Address 5 Address 9 Address 13 xxxxxxxxxxxxxxxx Y1 Y2 Ones concentrated in the systematic part at addresses {586, 587, 591, 650, 651,655, 763, 764, 768, 1019, 1020, 1024} Modification: {585, 587, 650, 651, 763 and 764} instead of {9, 101, 581, 925, 1029 and 1133}  The new minimum distance of the optimized 3D TC is 33 (compared to 7)

18 Electronics Department Ph.D defense, Monday 26 th September 2011page 17 EXIT chart of the 3D TC with λ = 1/8 at E b /N 0 =1.5 dB for code rate R = 2/3 EXIT chart of the 3D TC with λ = 1/8 at E b /N 0 =1.55 dB for code rate R = 2/3 EXIT chart analysis: convergence threshold of the 3D TC EXIT chart based convergence analysis:  Determination of the convergence threshold of the TC & 3D TC (1.49 for an 8-state binary TC and R =2/3)  Compute the loss of convergence  Larger λ  more significant loss

19 Electronics Department Ph.D defense, Monday 26 th September 2011page 18 EXIT chart analysis: convergence threshold of the time varying 3D TC(1/2) R = 2/3 λ = 1/4 E b /N 0 =1.57 dB Here E b /N 0 =1.57 dB < convergence threshold

20 Electronics Department Ph.D defense, Monday 26 th September 2011page 19 EXIT chart analysis: convergence threshold of the time varying 3D TC(2/2) R = 2/3 λ = 1/4 E b /N 0 =1.58 dB Convergence threshold:1.58 dB

21 Electronics Department Ph.D defense, Monday 26 th September 2011page 20 Error rate performance of time varying 3D TCs Time varying results for blocks of k = 1146 bits Transmission over AWGN channel Loss of convergence reduced by 50% from 0:18 dB to 0:09 dB

22 Electronics Department Ph.D defense, Monday 26 th September 2011page 21 An optimal value of L using EXIT charts?

23 Electronics Department Ph.D defense, Monday 26 th September 2011page 22 An optimal value of L using EXIT charts? L=60 E b /N 0 =1.6 dB

24 Electronics Department Ph.D defense, Monday 26 th September 2011page 23 3D TCs for high spectral efficiency transmissions Transmission scheme BICM approach Among the bits forming a symbol in M-QAM or M-PSK modulations, the average probability of error is not the same for all the bits Three constellation mappings: -Mapping uniformly distributed on the entire constellation -Systematic bits mapped to better protected places as a priority -Systematic bits (then if possible) post-encoded parity bits protected as a priority

25 Electronics Department Ph.D defense, Monday 26 th September 2011page 24 Example: 3D TCs associated with an 8-PSK modulator The third configuration cannot be adopted Systematic bits mapped to better protected places Significant gain: 0.5 dB k = 1146 bits R = 4/5 λ = 1/8 3 bits of an 8-PSK symbol 1146 x 143 y y w PSK symbols

26 Electronics Department Ph.D defense, Monday 26 th September 2011page 25 Decoding of irregular TCs Only one SISO The decoder computes the channel output LLRs Appropriate repetition to each LLR A posteriori probability Extrinsic information = product of d-1 extrinsics Appropriate likelihoods repetition SISO Decoder Systematic part Channel output APP Π Product of Extrinsic information

27 Electronics Department Ph.D defense, Monday 26 th September 2011page 26 Monte Carlo simulations Fixing a degree d Irreg and varying its fraction f Irreg A fraction that achieves the best performance can be found Changing the degree d Irreg, while the fraction is fixed to the value already selected We can then find optimal values for both d Irreg and f Irreg This profile is not automatically the best one: -Optimization does not take into account all the possible combinations ( d Irreg, f Irreg ) -Better performance may be attained when the profile is not restricted to two non-zero fractions Monte Carlo simulations are time consuming We propose a method based on the EXIT diagrams to select a good degree profile

28 Electronics Department Ph.D defense, Monday 26 th September 2011page 27 Determination of the degree profile using hierarchical EXIT charts Plot the EXIT diagrams for a finite block length Why? For infinite block lengths All the curves merge with one another -  We cannot distinguish between the different degree profiles For finite block sizes EXIT tool adapted Hierarchy between the different degree profiles Hypothesis: extrinsic information messages are i.i.d The aim is not to compute accurate convergence thresholds The method Simple Comparing many degree profiles at the same time Even profiles with more than two non-zero fractions

29 Electronics Department Ph.D defense, Monday 26 th September 2011page 28 Determination of the degree profile using hierarchical EXIT charts

30 Electronics Department Ph.D defense, Monday 26 th September 2011page 29 Determination of the degree profile using hierarchical EXIT charts

31 Electronics Department Ph.D defense, Monday 26 th September 2011page 30 Performance of irregular TCs Irregular TCs can achieve performance closer to capacity But very poor asymptotic performance Only one reference [1] deals with the problem of lowering the error floor of irregular TCs No previous work focused on optimizing the interleaver except in [2] Our interest: Not only large block lengths But also medium and short blocks Proposed solutions in [1,2] do not seem concrete Especially if only few iterations are required during the decoding process [1] H. Sawaya and J. Boutros. “Irregular turbo-codes with symbol-based iterative decoding”, 3rd International Symposium on Turbo-codes, Brest, France, September [2] G. M. Kraidy and V. Savin, “Capacity-approaching irregular turbo codes for the binary erasure channel,” IEEE Trans. Com., vol. 58, no. 9, pp. 2516–2524, September 2010.

32 Electronics Department Ph.D defense, Monday 26 th September 2011page 31 How to devise sophisticated permutations for irregular TCs? Example: Degree profile (f 2,f 8 ) f 2 = 5/6 and f 8 = 1/6 First idea: all the groups of 8 bits are uniformly distributed To avoid correlation  large spread between the pilot groups Empirical value for the spread: Constraint on f 8 :

33 Electronics Department Ph.D defense, Monday 26 th September 2011page 32

34 Electronics Department Ph.D defense, Monday 26 th September 2011page 33 Performance of irregular TCs with post- encoding All simulations use the MAP algorithm with 10 decoding iterations Degree profile (f 2,f 8 ), d av = 3, R = ¼ and k = 2046 bits 3GPP2 interleaver, interleaver size: 6138


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