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Testing of PLA and PAL. 111 +V... 0...... y1y1 y2y2 y m x 1 x 2 x n + V Buffer ANDOR......... x 1 x 2 x n y1y1 y2y2 y m PAL/PLA structure.

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Presentation on theme: "Testing of PLA and PAL. 111 +V... 0...... y1y1 y2y2 y m x 1 x 2 x n + V Buffer ANDOR......... x 1 x 2 x n y1y1 y2y2 y m PAL/PLA structure."— Presentation transcript:

1 Testing of PLA and PAL V y1y1 y2y2 y m x 1 x 2 x n + V Buffer ANDOR x 1 x 2 x n y1y1 y2y2 y m PAL/PLA structure

2 111 +V x 1 x 2 x 3 0 y 1 y 2 y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 Example.

3 1.Permanent constant faults; 2.Short-circuits; 3.Crosspoint Faults ; appearance of CP-s in the AND array;; disappearance of CP-s from the AND array; appearence of CP-s in the OR array; disappearance of CP-s from the OR array. Models of fault in PLA-s and PAL-s fXfX s-a-1s-a-0 f1X f2X Short Classical model of fault: constant 1 and 0 (Stuck-at-0, Stuck-at-1, s-a-0, s-a-1) f1 X X

4 111 +V x 1 x 2 x 3 0 y 1 y 2 y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 s-a-1 X 3 s-a-1fault y 1 = x 1 x 2 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 + x 1 x 2 Permanent constant faults in PLA/PAL-s

5 Crosspoint Faults Appearance of CP-s to in the AND array 111 +V x 1 x 2 x 3 0 y 1 y 2 y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 Unnecessary CP y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 x 3 y 2 = x 1 x 2 x 3 + x 1 x 2 x 3 Unnecessary variable Shrinkage fault Carnaugh Map x1x x2x3x2x3 y2y x1x x2x3x2x3 y2y2 FaultlessFaulty

6 Disappearance of CP-s from the AND array 111 +V x 1 x 2 x 3 0 y 1 y 2 y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 CP does not exist y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 Growth fault Carnaugh Map x1x x2x3x2x3 y2y x1x x2x3x2x3 y2y2 FaultlessFaulty CP does not exist

7 Appearance of a new CP to the OR-array 111 +V x 1 x 2 x 3 0 y 1 y 2 y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 Unnecessary CP y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 + x 1 x 2 x 3 Carnaugh Map x1x x2x3x2x3 y2y x1x x2x3x2x3 y2y2 FaultlessFaulty Appearance fault

8 111 +V x 1 x 2 x 3 0 y 1 y 2 y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 CP does not exist y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 Carnaugh Map x1x x2x3x2x3 y2y x1x x2x3x2x3 y2y2 FaultlessFaulty Disappearance fault Disapperance of the CP from the OR-array CP does not exist

9 Missing CP-s are equivalent to some constant faults (Stuck-at-0/1) but additional CP-s do not corrspond to that model. n – number of inputs m – number of terms k – number of outputs (2n + k) – different single and manifold CP faults different single and manifold CP faults (2n + k)m CP faults may be untestifyiable in case of excessive functions For example: y 1 = x 1 + x 2 + x 1 x 2 = x 1 + x 2 The missing of CP corresponding to whichever variable is not testifyiable in the AND array. The missing of CP corresponding to this term is not testifyiable in the OR array.

10 1.Traditional methods for circuits equivalent to PAL/PLA-s; 2.Random testing 3.Exhaustive testing 4.Semirandom methods 5.Deterministic Methods Generation of tests for PLA-s and PAL-s Traditional methods for equivalent circuits. & & 1 Cons: 1.Ineffective due to convergent branching 2. CP faults cannot be described as traditional s-a-0/1 faults.

11 Random testing & X s-a-0 00 & X s-a Discovery of the fault in AND array / /0 Bringing the impact of the fault to the output through OR array PAL/PLA Reactions Random combinations Cons: 1. A very large number of tests as in AND array combinations where only one input is 1 and the rest are 0s can be used as tests. 2.A very large number of tests as the transport through the OR array requires that one input equals 1 and the rest are 0s.

12 Exhaustive testing and semirandom methods PAL/PLA Reactions All possible combinations Cons: A large number of tests when real arrays are considered (for example, 50 inputs, 67 outputs, 190 terms) Exhaustive testing Semirandom method PAL/PLA Reactions Generator of pseudorandom numbers & Random numbers are not used. In stead, numbers with only one 0 are used.

13 Deterministic Test Generation Special algorithms oriented at the structure of the array and testing of CP-s V x 1 x 2 x 3 0 y 1 y 2 y 1 = x 1 x 2 x 3 + x 1 x 2 x 3 + x 1 x 2 y 2 = x 1 x 2 x 3 + x 1 x 2 Example: let us test whether x 1 x 2 has been Added in the function y 2 with CP x 3. Let us define the operation: a # b = a b Activating the impact of the fault: a = term that can be tested without faults b = term than can be tested with faults Example. x 1 x 2 # x 1 x 2 x 3 = x 1 x 2 (x 1 x 2 x 3 ) = x 1 x 2 x 3 Transport of the impact of the fault to the output: a =result of the previous operation, b =functiwithout the tested term Example.x 1 x 2 x 3 # x 1 x 2 x 3 = x 1 x 2 x 3 (x 1 x 2 x 3 ) = x 1 x 2 x 3 Test : x 1 = 1 x 2 = 1 x 3 = /

14 Testable PLA Design What is the objective? Concurrent testing Fault masking Special Design Self-testing Test generation Yes No Yes No Yes No YesNo Must be taken into consideration: 1.Indicators of testability; 2.Impact on the original design; 3.Requirements for the testing environment; 4.Cost of design

15 Buffer ANDOR x 1 x 2 x n y1y1 y2y2 y m Concurrent testing of PAL/PLA-s I Examples of testable PLA/PAL-s TSC Two-rail Checker fg Additional line TSC 1-out-of-m code checker Parity check fg faultless/faulty Totaly Self Cheking (TSC) Two-rail Checker x0x0 x1x1 y0y0 y1y1 x0x0 x1x1 y0y0 y1y1 f TSC Two-rail Checker fg g If x 0 = y 0 and x 1 = y 1 then f = g

16 Concurrent testing of PAL/PLA-s I (using the Berger code) Buffer ANDOR x 1 x 2 x n y1y1 y2y2 y m Additional lines TSC Two-rail Checker fg Control code generator Inverse value of the control code Control code

17 Berger code Orders of infoOrder of control (number of 0s in the code) 011 Control order generator Orders of info Orders of control Comparison scheme True/false Modifyied Berger code for a set of functions x 1 x x3x4x3x4 y1y x 1 x x3x4x3x4 y3y x 1 x x3x4x3x4 y2y x 1 x x3x4x3x4 c 1 c

18 PAL/PLA testable with universal tests ANDOR x 1 x n y1y1 y2y2 y ky k c1c1 c2c2 s1s1 smsm... s m+1 Parity check z1z1 Additional line Parity check Additional line z2z2 Selection of terms Decoder of the modified inputs Decoder of the modified inputs 1 & & b 2i-1 b 2i xixi c1c1 c2c2 It is possible to test an array without knowing how it has been programmed. The testing is not concurrent.

19 Universal tests e m = 0, if m is odd 1, if m is even The length of the tests is 1+m+n, where m is the number of terms and n is that of inputs.

20 A built-in Self-Testable PLA with Cumulative Parity Comparision AND (the number of used CP-s at each line must be odd)) OR (the number of used CP-s mt each line must be even) x 1 x n y1y1 y2y2 y ky k c1c1 c2c2 s1s1 smsm... s m+1 Additional line Parity check Additional line Selection of terms Decoder of the modified inputs xor T D z While transmitting universal tests (n+m+1) the trigger takes at each test series the opposite value according to the previous series.

21 Methods using signature LFSR - Linear Feedback Shift Register TT + TT + Signature Analyzer TT + TT +++ Parallel. Series TTTT + + Signal from the checked object Signals from the checked object

22 Buffer ANDOR x 1 x 2 x n y1y1 y2y2 y m LFSR (Generator of pseudorandom numbers) Signature analyzer I Signature analyzer II All possible input combinations may be used instead of the generator of pseudorandom numbers

23 PLA/PAL with BILBO-s. BILBO – Built-in Logic-Block Observer LFSR that can be activated as the generator of pseudorandom numbers or as signature analyzer (depending on the conditions chosen) Buffer ANDOR y1y1 y2y2 y m BILBO I BILBO II BILBO III...x 1 x 2 x n

24 More methods for improving the testability 1. Counting of CP-s. Presupposes the conductivity of bit lines and term lines. Presupposes that the expected CP numbers are known (functioning array) 2. feedback from the signature analyzer to the inputs (to the LFSR generating pseudorandom values). Thus ate these blocks united into one. 3. several signature analyzers are used for testing both the AND and OR part. For example, one is used for testing even bit lines and the other for odd. It results in the better use of the chip area as the analyzer behind the bit lines requires more space than the bit lines. 4. AND and OR arrays are divided into parts that enables to test them simultaneously. Presupposes that additional requirements are set for thr programming of PAL/PLA-s.


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