Download presentation

Presentation is loading. Please wait.

Published byJan Hopkin Modified over 2 years ago

1
Using Registers Ch.7 – p.158 Topic 1

2
Base - Displacement See page 159 PACKPDEC(3),ZDEC(3)

3
Base - Displacement Displacement Memory address distance from the most recent USING Length Number of bytes Base Register Established by BALR & USING. A program address is base + displacement

4
Add (Binary) Instruction Example:AREG,ONHND(IXREG)

5
Add Instruction Family (A, AR, AH) The second operand is added to the first operand, and the sum in placed at the first-operand location. The operands and the sum are treated as 32-bit (for AH, second operand is treated as 16-bit) signed binary integers. When there is an overflow, the result is obtained by allowing any carry into the sign-bit position and ignoring any carry out of the sign- bit position, and condition code 3 is set. If the fixed-point-overflow mask is one, a program interrupt for fixed-point overflow occurs. 0no overflow 1result 0, no overflow 3overflow

6
Subtract Instruction Example:SREG,ONORD(IREG)

7
Subtract Instruction Family (S, SR, SH) The second operand is subtracted from the first operand, and the difference is placed at the first-operand location. The operands and the difference are treated as 32-bit (SH, 2 nd operand is treated as 16-bit) signed-binary integers. When there is an overflow, the result is obtained by allowing any carry into the sign-bit position and ignoring any carry out of the sign- bit position, and condition code 3 is set. If the fixed-point-overflow mask is one, a program interruption for fixed-point overflow occurs. 0result 0, no overflow 1result 0, no overflow 3overflow

8
Multiply Instruction

9
Multiply Instruction Family (M, MR, MH) The second word of the first operand (multiplicand) is multiplied by the second operand (multiplier), and the double-word product is placed at the first operand location. For M, the R1 field designates a even-odd pair of GPRs and must designate an even-numbered register, otherwise a specification exception is recognized. Both multiplicand and multiplier are treated as 32-bit (for MH, multiplier is treated as 16-bit) signed binary integers. No condition codes are set. MR4,9 MULTIPLICAND MULTIPLIER 45 9 PRODUCT

10
Divide Instruction

11
DIVIDE Instruction Family (D, DR) The double-word first operand (dividend) is divided by the second operand (divisor), and the remainder and the quotient are placed at the first operand location. The R1 field designates an even-odd pair of GPRs and must designate an even-numbered register, otherwise a specification exception is recognized. The dividend is treated as a 64-bit signed binary integer, The divisor, the remainder, and the quotient are treated as 32-bit signed binary integers. The remainder is placed in R1 and the quotient is placed in R1+1. DR6,9 REMAINDER DIVISOR QUOTIENT 9 67

12
COMPARE Instruction

13
COMPARE Instruction Family (C, CR, CH) The first operand is compared with the second operand, and the result is indicated in the condition code. The operands are treated as 32-bit signed binary integers 0operands are equal 1first operand is low 2first operand is high 3- - - - CR5,8 CWEEK-HRS,40HRS

14
BRANCH ON COUNT

15
BRANCH ON COUNT Instruction family (BCT, BCTR) One is subtracted from the first operand, and the result is placed at the first-operand location. The first operand and result are treated as 32-bit binary integers with overflow ignored. When the result is zero, normal instruction execution sequencing proceeds with the updated instruction address. When the result is not zero, the instruction address in the current PSW is replaced by the branch address (the second operand). In the 2-byte format, if R2 operand is zero, no branch is taken, however one is still subtracted from R1 The condition code is not used. BCT3,LOOP

16
CONVERT TO BINARY Converts a Packed Decimal number to Binary Result is stored in the register (first operand) 2 nd operand (B2,D2) must be 8 bytes

17
CVB CVBR1,D2(X2,B2) CVB7,PDECIMAL --- PDECIMALDCXL8’000000000000256F’

18
CONVERT TO DECIMAL Reverse of Convert to Binary Converts binary value in a register to packed decimal format and stores it in 8 bytes

19
CVD CVDR1,(D2(X2,B2) L6,HUNDRED CVD6,BINVALU - - BINVALUDSPL8 HUNDREDDCF’256’*00 00 01 00

20
NUM is a 2-byte field with a value between 01 and 10. It is read in from an input file. It is used to index into a table with 10 different hourly salaries and NUM is consistent with the salary code number from a time-card. NUM must be in binary format to be used as an index. Reg 7 contains the address on memory of the pay rate table (not shown) and each entry in the table is 5-bytes. The paycode is read in, PACKed and converted to binary. The appropriate table entry corresponding to the code is accessed and the pay rate is outputted to the monitor with a WTO instruction.

21
COMPARE LOGICAL Compare Logical Characters(CLC) –6-byte instruction format (SS) –CLCD1(L,B1),D2(B2) –Compare up to 256 characters Compare Logical Immediate(CLI) –4-byte instruction format (SI) –CLID1(B1),I2 –Compare a single byte

22
CLC, CLI Different than arithmetic compare instructions – all characters are unsigned CLI compares a single byte in memory with a single byte that is included with the instruction (I2 field) CLC compares a byte at a time left-to-right (low-to-high) Both Compare instructions set the condition code

23
CLC, CLI Condition Code: 0operands are equal 1first operand low 2first operand high 3- - - CLIAB+10,C’C’ D1 D6 C8 D5 E2 D6 D5 6B C1 4B C2 4B D1 D6 C8 D5 E2 D6 D5 6B C1 4B C3 4B AB AC What is the CC that is set? ____________ 1

24
MOVE Instructions Move Characters(MVC) Move Immediate(MVI) Move Numerics(MVN) Move Zones(MVZ) Second operand is placed at the first operand location – left-to-right

25
Move Characters (MVC) MVCD1(L,B1),D2(B2) Move up to 256 bytes from 2 nd operand to the 1 st operand Examples: –MVCOUTAREA(80),INAREA –MVCOUTPRICE(5),UNITCOST

26
Move Immediate(MVI) MVID1(B1),I2 Moves a single character from the 2 nd operand to the 1 st operand 2 nd operand is data within the instruction MVIOUTPRICE+0,c’$’

27
Move Numerics(MVN) Generally, used with zoned-decimal data – moves only the numeric part of the byte (not the zones) C6 C7 C8 C9 FLDA F0 F1 F2 F3 F4 F5 FLDB MVNFLDB(4),FLDA C6 C7 C8 C9 FLDA F6 F7 F8 F9 F4 F5 FLDB

28
Move Zones(MVZ) Generally, used with zoned-decimal data – moves only the zones part of the byte (not the numerics) C6 C7 C8 C9 FLDA F0 F1 F2 F3 F4 F5 FLDB MVZFLDB(4),FLDA C6 C7 C8 C9 FLDA C0 C1 C2 C3 F4 F5 FLDB

29
Defining Binary Data Page 162 in your textbook Examples: FWDCF’1’* 00 00 00 01 * HWDCH’123’* 00 78 * FWNDCF’-123’* FF FF FE DD* DWDSD FW4DS4F HW3DS3H

30
Defining Address Constants DCBADDDCA(INDCB) INBUFADDDCA(INBUFFER) INDCB INBUFFER INDCB

31
Multiple Instructions Load Multiple (LM) Store Multiple(STM)

32
READING ASSIGNMENT Read Ch.7 – Topic 1 But, you do not need to read the section called “Some System/370 Instructions” beginning on page 170 through the end of the Topic – page 175. But you can read the section if you want.

33
More About Binary Arithmetic Ch.7 Topic 2 Page 176

34
Working with Negative Numbers Let’s say you have a numeric value in a register, but you don’t know if it’s positive or negative. How can you tell? Is the number in the register above positive or negative? _______________ How can you tell? _____________________________________ 80 00 00 33 negative High-order bit is set to one.

35
How Can You Tell? Registers are 32 bits in length 31 bits are used to represent values High-order (left-most) bit is used to identify the sign –Bit is “1” represents a negative value –Number is in 2’s complement format (2’s complement format essentially is the bits are flipped – 1 bits become 0 and 0 bits become 1

36
How Does It Work? High-order bit is “1” – value is negative Flip all the bits from 1 to 0 or from 0 to 1 Then add 1 Result is negative 123 FF FF FE DD 00 00 01 22 00 00 01 23

37
Can You Convert the Other Way? To convert a positive binary value: Subtract 1 from the original value Flip all the bits 00 00 01 23 = FF FF FE DD 0000 0001 0010 00111111 1110 1101 1101 0000 0001 0010 0010 - 1

38
So How Do I Test the High-Order Bit? If the value is in memory, use TM Test Under Mask instruction 4-byte format (SI)

39
Test Under Mask(TM) TM examines selected bits of a byte and sets the condition code 0selected bits are all zeros 1selected bits mixed zeros & ones 2- - - 3selected bits are all ones What bits are examined? The 1-bits in the Mask field TMVALUE,X’C1’MASK= 1100 0001 BZBITSOFFALL BITS OFF BOBITSONALL BITS ON BMBITSMIXDBITS ON AND OFF : VALUEDCXL4’E7B3C1F2’ Which branch is taken? _________________________ BITSON

40
Extended Mnemonics for TM Branch Instruction Extended Mnemonic Meaning BC 1BOBranch on Ones BC 4BMBranch on Mixed BC 8BZBranch on Zeroes BC 14BNOBranch Not Ones BC 11BNMBranch Not Mixed BC 7BNZBranch Not Zeroes

41
Binary Arithmetic Assignment Using your Carlton Realtors program, change the decimal arithmetic to binary arithmetic accomplishing the same as you did using decimal arithmetic. Due: next week

Similar presentations

Presentation is loading. Please wait....

OK

Microprocessors.

Microprocessors.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google