# Lecture 4. Topics covered in last lecture Multistage Switching (Clos Network) Architecture of Clos Network Routing in Clos Network Blocking Rearranging.

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Lecture 4

Topics covered in last lecture Multistage Switching (Clos Network) Architecture of Clos Network Routing in Clos Network Blocking Rearranging Algorithm

Strictly Non-blocking Clos Network For some applications the delay/modifications caused by the rearrangement algorithm is unacceptable To design the Clos network to be non-blocking, we need to increase the number of 2 nd stage switches (m) m  2n-1 Speedup ratio = m/n = 2 – 1/n Usually m = 2n in practical systems

Proof Assume we have a C(n, m, r) Assume in a 1 st stage switch, n-1 inputs are busy Assume in a 3 rd stage switch, n-1 outputs are busy Worst case, we want to connect the n th input to the n th output Set of busy 2 nd stage switches carrying connections from the n-1 inputs (S I ) contains n-1 elements Set of busy 2 nd stage switches carrying connections to the n-1 outputs (S O ) contains n-1 elements Set of 2 nd stage switches we cannot use = S I  S O

Proof N(S I  S O ) = N(S I ) + N(S O ) – N(S I  S O ) Where N(Y) is the number of elements in the set Y The left hand side is maximum when S I  S O =  Hence N(S I  S O ) max = 2n-2 So if there is only one more 2 nd stage switch, we can make the connection  m  2n-1

Number of Cross Connections We used Clos networks to reduce the complexity of switches Single stage switches have cross connections = N 2 Clos networks C(n, m, r): 1 st stage, r switches each n  m  r  n  m 2 nd stage, m switches each r  r  m  r  r 3 rd stage, r switches each m  n  r  m  n Total cross connection (N x ) = 2r  n  m + m  r 2 N x = 2m  N + m  (N/n) 2 = m(2N + (N/n) 2 ) For fair comparison, strictly non-blocking (m = 2n-1) N x = (2n-1)(2N + (N/n) 2 )

Number of Cross Connections Reduction ratio = N x /N 2 = m(2/N + (1/n) 2 ) m = 2n-1  = (2n-1)(2/N + (1/n) 2 ) Inputs (N)Number of Cross Connections Reduction Ratio ( ) Single StageClos Network (n = (0.5N) 1/2 ) 128 16,3847,6800.46875 512 262,14463,4880.2421875 2048 4,194,304516,0960.123046875 8192 67,108,8644,161,5360.062011719 32768 10,73,741,82433,423,3600.03112793 131072 17,179,869,184267,911,1680.015594482

Probability of Blocking Recall that blocking is the event that a connection is requested but the switch cannot connect it For strictly non-blocking switches this never happens (Probability = 0) For other switches, the probability is not 0 There are several methods to calculate this probability of blocking among them: Lee’s graphs: simple but not very accurate Jacobaeus method: accurate but complicated

Lee’s Graphs Case 1: i parallel links Assume: p is the probability that a link is busy q is the probability that a link is idle q = 1-p Since any link works the call is blocked only when all links (i) are busy The probability of blocking (B) is the probability of finding all links busy B = p i p p p p p … In Out

Lee’s Graphs Case 2: j serial links Assume: p is the probability that a link is busy q is the probability that a link is idle q = 1-p The call is connected only when all (j) links are idle The probability of success (S) is the probability of finding all links idle S = q j B = 1-S = 1-q j = 1-(1-p) j In Out q q q

Lee’s Graphs Case 3: i parallel, j serial Probability of blocking for any serial link = 1 – q j Probability of blocking for i parallel links = (B any link ) i Overall probability of blocking = (1-q j ) i = (1-(1-p) j ) i For Clos networks j = 2, i = m Prob. of Blocking = (1-(1-p) 2 ) m In Out q q q q q q q q q

Lee’s Graphs p is the probability that the link inside the switch (i.e. between stages 1 and 2 or 2 and 3) is busy This probability cannot be easily obtained It is easier to get the probability that the input link is busy (p in ) This can be calculated from the traffic generated by the users The internal probability (p) is then calculated from p in as follows:

Lee’s Graphs 1 st stage switches have n inputs each with p in busy probability and m outputs with p busy probability Probability that a link is busy  1/No of links p in  1/n p  1/m p  1/n = p in  1/m p = p in  n/m = p in /(m/n) B = (1-(1-p) 2 ) m

Jacobaeus Method Lee’s graphs Simple Directly related to the network architecture Identifies weaknesses of the network Not accurate Jacobaeus method More accurate and more complicated

Other Crossbar Switches Modern networks use optical fiber with laser/LED transmitters To use the previous switches, the signal (light) is converted to electrical signal, switched then converted to light again This scheme is inefficient and costly The aim is for an optical crossbar

Optical Crossbar Switches MEM Switch

Micro Electrical Mechanical System (MEMS) Switches Advantages No need for optical to electrical to optical (O-E-O) signal conversion Less delay and higher capacity Disadvantages Broadcast and multicast not possible

Digital Time Switch Consists of buffers and memory Data is transmitted serially and stored one bit every clock pulse in a shift register (buffer) After the buffer is full, all bits are transferred in parallel to another buffer This buffer holds the data until it’s turn to be written to the memory comes Memory locations are read, according to some control mechanism, and loaded into a buffer then into a shift register Bits are transmitted one at a time every clock pulse

Digital Time Switch Buffer I1 Buffer I2 Buffer IGIG … … … Memory G locations each B bits Bits enter serially, 1 bit every clock pulse (edge) All bits are transferred to the buffer and afterwards memory in one pulse edge Cyclic write Random read I4I1H…I2I4I1H Frame Header if any Time slot (B bits) B bits

Digital Time Switch The previous system requires a memory that can be written into and read from at the same time To overcome this two memories are used (say M1 and M2) First the switch writes in M1 while reading from M2 Then it writes in M2 while reading from M1 The same system works in the opposite direction (demultiplexing)

Digital Time Switch Cyclic and memory based controls are used The same sequence of time slots is maintained as long as the connection lasts Time slots in a frame are always of the same size A user can be assigned several time slots The frame duration is always constant throughout the whole network Strict synchronization requirements must be met It is possible to multiplex TDM frames (higher levels)

Digital Time Switch Buffer I1 Buffer I2 … … …I4 1 I1 2 I4 2 H2H2 I3 1 H1H1 H …I2 2 I4 2 I1 2 H2H2 …I4 1 I2 1 I3 1 H1H1 Memory X locations each B bits 2-Input Time Switch

Plesiochronous Digital Hierarchy (PDH) A somewhat old system for telephone networks Uses TDM and time switches Two standards are used US and European (also Japanese) European Standard 30 users are multiplexed + 2 signaling time slots (8 bits each) Frame duration 125  s Each user/time slot is equivalent to 64kbps 32 time slots * 64kbps = 2Mbps (E1) 4 frames of 2Mbps are multiplexed + signaling => 8,448kbps (8Mbps) 4 frames 8Mbps (or 16 2Mbps frames) + signaling => 34Mbps 4 frames 34Mbps => 140Mbps 4 frames 140 Mbps => 565 Mbps (not widely used) Bit interleaving is used for levels more than 2Mbps

Plesiochronous Digital Hierarchy (PDH) US Standard Uses 24 time slots for level 1 instead of 32 users Bit rate then becomes 1.544 Mbps (T1) instead of 2Mbps Higher rates are 1.544 Mbps *4 =>6.321 Mbps 6.321 Mbps * 7 => 44.736 Mbps 44.736 Mbps * 6 => 274.176 Mbps Japanese Standard Identical to US till the 6.321 Mbps 6.321 Mbps * 5 => 32.064 Mbps 32.064 Mbps * 3 => 97.728 Mbps 97.728 Mbps * 5 => 397.200 Mbps

Time and Space Switching The previous time switching examples assume we have several inputs (outputs) and a single output (input) Typically this is not the case, we can have several inputs and several outputs (specially middle of network) We can have several TDM inputs that must be switched to TDM outputs on different ports

Digital Time and Space Switch I1 I2 I2 1 I3 2 I1 1 H …I3 2 I2 2 I1 2 H2H2 …I3 1 I2 1 I1 1 H1H1 Time & Space Switch …I1 2 I3 1 I2 2 H

Digital Time and Space Switch Note that the slot ordering is not necessarily the same as the input The input and output ports are not fixed but change with time Such a switch consists of two stages A Time Switch : To rearrange the time slots A Space Switch: To switch from input ports to output ports

Time Switch Known as Time Slot Interchange (TSI) Basically rearranges the time slots in a frame Consists of a memory, buffers and control units E.g. cyclic write with random read …I6I5I4I3I2I1 TSI …I3I1I6I8I2I4

Space Switch A crossbar switch with an extra external memory and a counter The external memory stores the crossbar configuration for each time slot The counter selects which configuration to load into the crossbar

Space Switch N  N Xbar TS 0 Config. TS 1 Config. … TS G Config. Modulo G Counter … 1 2 N 1 2 N … … … Memory of Xbar Configurations Control (Programming) Lines

T-S Switch One TSI for each input One Space Switch TSI Buffer I1 I2 TSI Buffer 2  2 Switch

T-S Switch Operation Example I6I5I4I3I2I1 I6I5I4I3I2I1 221211 Output Port 211221 Input 1 Input 2 TSI I6I5I4I3I2I1 211221 Output Port I4I6I5I2I1I3 122112 Output Port Not the same output at the same time slot

T-S Switch Operation I6I5I4I3I2I1 211221 Output Port I4I6I5I2I1I3 122112 Output Port N  N Xbar 1-1, 2-2 1-2, 2-1 1-1, 2-2 1-2, 2-1 Modulo 6 Counter I4I5I4I2I1 211221 Input Port I6 I5I3I2I3 122112 Input Port

T-S Switch A TS switch changes the order of the time slots so that the space switch can forward the data from the input to the output ports If the connection status change, the order of the output time slots may also change In the previous example, assume the connections I1 and I3 from input 1 are terminated and new connections from I1 to output 2 and from I3 to output 1 are created

Example Original Connections I6I5I4I3I2I1 I6I5I4I3I2I1 221211 Output Port 211221 Input 1 Input 2 TSI I6I5I4I3I2I1 211221 Output Port I4I6I5I2I1I3 122112 Output Port

Example New Connection I6I5I4I3I2I1 I6I5I4I3I2I1 221211 Output Port 211122 Input 1 Input 2 TSI I6I5I4I3I2I1 211122 Output Port I4I6I5I3I2I1 122211 Output Port

Example I6I5I4I3I2I1 211122 Output Port I4I6I5I3I2I1 122211 Output Port N  N Xbar 1-2, 2-1 1-1, 2-2 1-2, 2-1 Modulo 6 Counter I4I5I4I3I2I1 211122 Input Port I6 I5I3I2I1 122211 Input Port

Example Note that the order of the slots in the output frames changed although only two slots in the input frames changed I4I5I4I2I1 211221 Input Port I6 I5I3I2I3 122112 Input Port I4I5I4I3I2I1 211122 Input Port I6 I5I3I2I1 122211 Input Port Original Order New Order Output port 1 Output port 2

TST Switch The change in slot order is a problem since typically these slots are forwarded to another switch which was already programmed according to the original order The problem can be solved by signaling the next switch about the order change but this Requires more signaling overhead Increases processing loads if call rate is high Can cause network instability (changes cause more changes) A better solution is to add another TSI after the space switch to return the slot order to its initial order!!

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