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Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Overview n Why VLSI? n Moore’s Law. n The VLSI design process. n IP-based design.

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Presentation on theme: "Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Overview n Why VLSI? n Moore’s Law. n The VLSI design process. n IP-based design."— Presentation transcript:

1 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Overview n Why VLSI? n Moore’s Law. n The VLSI design process. n IP-based design.

2 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Why VLSI? n Integration improves the design: –lower parasitics = higher speed; –lower power; –physically smaller. n Integration reduces manufacturing cost- (almost) no manual assembly.

3 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall VLSI and you n Microprocessors: –personal computers; –microcontrollers. n DRAM/SRAM. n Special-purpose processors.

4 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Moore’s Law n Gordon Moore: co-founder of Intel. n Predicted that number of transistors per chip would grow exponentially (double every 18 months). n Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

5 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Moore’s Law plot

6 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Moore’s Law and Intel processors

7 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Moore/Intel log scale

8 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Terminology n Manufacturing node: technology at a particular channel length. n Deep submicron technology: nm. n Nanometer technology: 100 nm and below.

9 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall The cost of fabrication n Current cost: $4 billion. n Typical fab line occupies about 1 city block, employs a few hundred people. n Most profitable period is first 18 months-2 years.

10 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Cost factors in ICs n For large-volume ICs: –packaging is largest cost; –testing is second-largest cost. n For low-volume ICs, design costs may swamp all manufacturing costs.

11 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Cost of design n Design cost can be significant: $20 million for a large ASIC, $500 million for a large CPU. n Cost elements: –Architects, logic designers, etc. –CAD tools. –Computers the CAD tools run on.

12 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Intellectual property n Intellectual property (IP): pre-designed components. –May come from outside vendors, internal sources. n IP saves time, design cost. n IP blocks must be designed to be reused.

13 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Reliability n Nanometer technologies require attention to reliability. n Design-for-manufacturing (DFM) and design-for-yield (DFY) techniques adjust the design to improve yield. n Circuit and architecture techniques can compensate for unreliable components.

14 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall The VLSI design process n May be part of larger product design. n Major levels of abstraction: –specification; –architecture; –logic design; –circuit design; –layout.

15 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Challenges in VLSI design n Multiple levels of abstraction: transistors to CPUs. n Multiple and conflicting constraints: low cost and high performance are often at odds. n Short design time: Late products are often irrelevant.

16 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Dealing with complexity n Divide-and-conquer: limit the number of components you deal with at any one time. n Group several components into larger components: –transistors form gates; –gates form functional units; –functional units form processing elements; –etc.

17 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Hierarchical name n Interior view of a component: –components and wires that make it up. n Exterior view of a component = type: –body; –pins. Full adder a b cin sum cout

18 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Instantiating component types n Each instance has its own name: –add1 (type full adder) –add2 (type full adder). n Each instance is a separate copy of the type: Add1(Full adder) a b cin sum cout Add2(Full adder) a b cin sum Add1.a Add2.a

19 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall A hierarchical logic design z box1box2x

20 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Net lists and component lists n Net list: net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out n Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet

21 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Component hierarchy top i1xxxi2

22 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Hierarchical names n Typical hierarchical name: –top/i1.foo component pin

23 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Layout and its abstractions n Layout for dynamic latch:

24 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Stick diagram

25 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Transistor schematic

26 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Mixed schematic inverter

27 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Levels of abstraction n Specification: function, cost, etc. n Architecture: large blocks. n Logic: gates + registers. n Circuits: transistor sizes for speed, power. n Layout: determines parasitics.

28 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Circuit abstraction n Continuous voltages and time:

29 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Digital abstraction n Discrete levels, discrete time:

30 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Register-transfer abstraction n Abstract components, abstract data types:

31 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Top-down vs. bottom-up design n Top-down design adds functional detail. –Create lower levels of abstraction from upper levels. n Bottom-up design creates abstractions from low-level behavior. n Good design needs both top-down and bottom-up efforts.

32 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Design abstractions specification behavior register- transfer logic circuit layout English Executable program Sequential machines Logic gates transistors rectangles Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns functioncost

33 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Design validation n Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. n Forward checking: compare results of less- and more-abstract stages. n Back annotation: copy performance numbers to earlier stages.

34 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Manufacturing test n Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right. n Must quickly check whether manufacturing defects destroy function of chip. n Must also speed-grade.

35 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall IP-based design n Almost every chip uses some form of IP: –Standard cell libraries. –Memories. –IP blocks. n Designers must know how to: –Create IP. –Use IP.

36 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Types of IP n Hard IP: –Pre-designed layout. –Allows more detailed characterization. n Soft IP: –No layout---logic synthesis, etc. –IP layout is created by the IP user.

37 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Hard IP n Must conform to many standards: –Layout pin placement. –Layer usage. –Transistor sizing. n Hard IP blocks are usually qualified on a particular process. –Component is fabricated and tested to show that the IP works on that fab line.

38 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Soft IP n Conformance of layout to local standards is easier since it is created by the user. n Timing can only be estimated until the layout is done. n Must conform to interface standards. –A wrapper adapts a block to a new interface.

39 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall IP across the design hierarchy n Standard cells. –Pitch matched in rows, compatible drive. n Register-transfer modules. n Memories. n CPUs. n Busses. n I/O devices.

40 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Specifying IP n Hard or soft? n Functionality. n Performance, including process corners. n Power consumption. n Special process features required.

41 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall The I/O lifecycle spec HDL design validationdocumentationextraction qualification IP modules chip design IP database IP docs

42 Modern VLSI Design 4e: Chapter 1 Copyright  2008 Prentice Hall Using IP n May come from vendor, open source, or internal group. n Must identify candidate IP, evaluate for suitability. n May have to pay for IP. n May want to qualify IP before use, particularly if it pushes analog characteristics.


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