2 Why VLSI? Integration improves the design: lower parasitics = higher speed;lower power;physically smaller.Integration reduces manufacturing cost-(almost) no manual assembly.
3 VLSI and you Microprocessors: DRAM/SRAM. Special-purpose processors. personal computers;microcontrollers.DRAM/SRAM.Special-purpose processors.
4 Moore’s Law Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 months).Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.
8 TerminologyManufacturing node: technology at a particular channel length.Deep submicron technology: nm.Nanometer technology: 100 nm and below.
9 The cost of fabrication Current cost: $4 billion.Typical fab line occupies about 1 city block, employs a few hundred people.Most profitable period is first 18 months-2 years.
10 Cost factors in ICs For large-volume ICs: packaging is largest cost;testing is second-largest cost.For low-volume ICs, design costs may swamp all manufacturing costs.
11 Cost of designDesign cost can be significant: $20 million for a large ASIC, $500 million for a large CPU.Cost elements:Architects, logic designers, etc.CAD tools.Computers the CAD tools run on.
12 Intellectual property Intellectual property (IP): pre-designed components.May come from outside vendors, internal sources.IP saves time, design cost.IP blocks must be designed to be reused.
13 Reliability Nanometer technologies require attention to reliability. Design-for-manufacturing (DFM) and design-for-yield (DFY) techniques adjust the design to improve yield.Circuit and architecture techniques can compensate for unreliable components.
14 The VLSI design process May be part of larger product design.Major levels of abstraction:specification;architecture;logic design;circuit design;layout.
15 Challenges in VLSI design Multiple levels of abstraction: transistors to CPUs.Multiple and conflicting constraints: low cost and high performance are often at odds.Short design time: Late products are often irrelevant.
16 Dealing with complexity Divide-and-conquer: limit the number of components you deal with at any one time.Group several components into larger components:transistors form gates;gates form functional units;functional units form processing elements;etc.
17 Hierarchical name Interior view of a component: components and wires that make it up.Exterior view of a component = type:body;pins.coutFulladdersumabcin
18 Instantiating component types Each instance has its own name:add1 (type full adder)add2 (type full adder).Each instance is a separate copy of the type:coutAdd1.aAdd2.aAdd2(Fulladder)Add1(Fulladder)sumsumaabbcincin
27 Levels of abstraction Specification: function, cost, etc. Architecture: large blocks.Logic: gates + registers.Circuits: transistor sizes for speed, power.Layout: determines parasitics.
28 Circuit abstractionContinuous voltages and time:
29 Digital abstractionDiscrete levels, discrete time:
30 Register-transfer abstraction Abstract components, abstract data types:0010+0001+00110100
31 Top-down vs. bottom-up design Top-down design adds functional detail.Create lower levels of abstraction from upper levels.Bottom-up design creates abstractions from low-level behavior.Good design needs both top-down and bottom-up efforts.
33 Design validationMust check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it.Forward checking: compare results of less- and more-abstract stages.Back annotation: copy performance numbers to earlier stages.
34 Manufacturing testNot the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right.Must quickly check whether manufacturing defects destroy function of chip.Must also speed-grade.
35 IP-based design Almost every chip uses some form of IP: Standard cell libraries.Memories.IP blocks.Designers must know how to:Create IP.Use IP.
36 Types of IP Hard IP: Soft IP: Pre-designed layout. Allows more detailed characterization.Soft IP:No layout---logic synthesis, etc.IP layout is created by the IP user.
37 Hard IP Must conform to many standards: Layout pin placement.Layer usage.Transistor sizing.Hard IP blocks are usually qualified on a particular process.Component is fabricated and tested to show that the IP works on that fab line.
38 Soft IPConformance of layout to local standards is easier since it is created by the user.Timing can only be estimated until the layout is done.Must conform to interface standards.A wrapper adapts a block to a new interface.
39 IP across the design hierarchy Standard cells.Pitch matched in rows, compatible drive.Register-transfer modules.Memories.CPUs.Busses.I/O devices.
40 Specifying IP Hard or soft? Functionality. Performance, including process corners.Power consumption.Special process features required.
42 Using IP May come from vendor, open source, or internal group. Must identify candidate IP, evaluate for suitability.May have to pay for IP.May want to qualify IP before use, particularly if it pushes analog characteristics.