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Cases 2007 Florida State University Chris Zimmer, Steve Hines, Prasad Kulkarni Gary Tyson, David Whalley Facilitating Compiler Optimizations Through the.

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Presentation on theme: "Cases 2007 Florida State University Chris Zimmer, Steve Hines, Prasad Kulkarni Gary Tyson, David Whalley Facilitating Compiler Optimizations Through the."— Presentation transcript:

1 Cases 2007 Florida State University Chris Zimmer, Steve Hines, Prasad Kulkarni Gary Tyson, David Whalley Facilitating Compiler Optimizations Through the Dynamic Mapping of Alternate Register Structures

2 Motivation 2 Embedded Processors have fewer registers. Compiler Optimizations increase register pressure Difficult to apply aggressive compiler optimizations on embedded systems

3 Vector Multiply Example 3 Even before aggressive optimizations, 60% of available registers are already used Further optimizations like Loop Unrolling and Software Pipelining are inhibited int A[1000], B[1000]; void vmul() { int I; for (I=2; I < 1000; I++) B[I] = A[I] * B[I-2]; }.L3: ldrr1,[r2,r3, lsl #2] ldrr12,[r4], #4 mulr0,r12,r1 strr0,[r5,r3, lsl #2] addr3,r3,#1 cmpr3, #1000 blt.L3

4 Application Configurable Processors 4 Exploit common reference patterns found in code Small register files mimic these reference behaviors. Map Table provides register redirection. Changed architecture to add more registers, but have minimal impact on ISA support, particularly not increasing operand size

5 Architectural Modifications 5 Register File Queue Q1 Queue Q2 Queue Q3 Stack Q4 Circular Buffer Q5 Map Table R6 R0 R1Q1 R15

6 Software Pipelining 6 Software pipelining is not often found in embedded compilers. Software pipelining reduces the overall cycle time of a loop. Extracts iterations Consumes Stalls Consumes registers!!

7 Software Pipelining Example 7 Stalls Present when Loop Run.L3: ldr r1,[r2,r3, lsl #2] ldr r12,[r4], #4 stall mul r0,r12,r1 stall str r0,[r5,r3, lsl #2] add r3,r3,#1 cmp r3, #1000 bgt.L3 int A[1000], B[1000]; void vmul() { int I; for (I=2; I < 1000; I++) B[I] = A[I] * C[I]; }.L3: ldrr1,[r2,r3, lsl #2] ldrr12,[r4], #4 mulr0,r12,r1 strr0,[r5,r3, lsl #2] addr3,r3,#1 cmpr3, #1000 blt.L3

8 Instruction 8 Goal: Minimal modification to existing instruction set. Single cycle instruction latency Method: Add a single instruction to the ISA that is used to map and unmap a common register specifier into a customized register structure. qmap qmap r3,#4,q3

9 Architectural Modifications 9 Register File Queue Q1 Queue Q2 Queue Q3 Destructive Queue Q4 Circular Buffer Q5 Map Table R6 R0 An access to R0, which has no mapping in the table would get the data from the register file. R1 is mapped into Q1 and would retrieve its data from there. R0 R1Q1 R15

10 4 30 Software Pipelining Example Q1 Q2 530 Q3 int A[1000], B[1000]; void vmul() { int I; for (I=2; I < 1000; I++) B[I] = A[I] * C[I]; }

11 Register Usage 11

12 Results – Multiplies varying latency, load latency set at four 12

13 Results – Loads varying latency, multiply latency set at four 13

14 Conclusions 14 Customized register structures reduce register pressure. Software pipelining is viable in resource constrained environments Performance can be improved with minor impact to the ISA.

15 Extra’s

16 Reference Behaviors 16 ldr r1,[r6,r4, lsl #4] ldr r12,[r6,r4, lsl #8] ldr r8,[r6,r4, lsl #12] str r8,[r3,r4, lsl #16] str r12,[r3,r4, lsl #20] str r1,[r3,r4, lsl #24] Stack Reference Behavior

17 Application Configurable Architecture 17 Application configurable processors are designed using a mapping table similar to a register rename table found in many out of order implementations. The map table is read during every access to the architected register file. This serves as a method of determining if a register specifier is used in the original architected register file or a customized register structure.

18 Application Configurable Architecture 18 The customized register files are small in size but they efficiently manage the values that would require many architected registers. The customized register files can mimic queues, stacks, and circular buffers. These structures are accessed using the same register specifier that is used to access the architected register file.

19 Remove Reference Behaviors 19 ldr r1,[r6,r4, lsl #4] ldr r12,[r6,r4, lsl #8] ldr r8,[r6,r4, lsl #12] str r8,[r3,r4, lsl #16] str r12,[r3,r4, lsl #20] str r1,[r3,r4, lsl #24] Stack Reference Behavior R8 R12 R1 r1 ldr r1,[r6,r4, lsl #4] ldr r1,[r6,r4, lsl #8] ldr r1,[r6,r4, lsl #12] str r1,[r3,r4, lsl #16] str r1,[r3,r4, lsl #20] str r1,[r3,r4, lsl #24] Free up r8 and r12 for use.

20 Remove Qmap Instruction 20 R8 R12 R1 q0 Free up r8 and r12 for use.

21 Modulo Scheduling 21 For our work we used modulo scheduling. This requires using the dependences and latencies of the loop instructions to generate a modulo scheduled loop. The prolog and epilog are then built based off of this schedule. The prolog and epilog in require register renaming of loop carried dependencies to verify a correct loop. Renaming in embedded processors is often not possible.

22 Register Renaming due to software pipelining 22 Renaming doesn’t work… not enough registers. Rotating registers would require a significant rewrite of the embedded ISA. The loop carried values can simply be mapped into a register queue to hold the value across several iterations.

23 Results Register Savings 23 As latency grows for the instructions more iterations of the loop are extracted to spread out the latency. The extra registers that would be required to perform renaming have measured from 25% to 200% of the available registers in the ARM.


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