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Chapter 2 Sections 2.1 – 2.10 Based on slides from Dr. Iyad F. Jafar Instructions: Language of the Computer.

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Presentation on theme: "Chapter 2 Sections 2.1 – 2.10 Based on slides from Dr. Iyad F. Jafar Instructions: Language of the Computer."— Presentation transcript:

1 Chapter 2 Sections 2.1 – 2.10 Based on slides from Dr. Iyad F. Jafar Instructions: Language of the Computer

2 Outline The Von Neumann Architecture Busses & Memory Program Execution The Computer Language Instruction Set Architecture The MIPS ISA MIPS Design Principles Fallacies and Pitfalls Further Reading More Examples 2

3 The Von Neumann Architecture 3 John Von Neumann,1945 A computer consists of Processor Memory Input and Output Stored-program concept as opposed to program- controlled computers ! Programs and data are loaded into memory prior to execution Different components are connected via set of shared wires called Busses for information exchange Compare to Harvard Architecture! Processor Memory Devices Datapath Control Input Output

4 Busses In any computer, there is usually three types of busses Data Used to exchange data between components Bidirectional Typical size 8, 16, 32, and 64 bits Address Used to specify the source/destination Unidirectional The size of the bus specifies the number of entities (memory locations,I/O) that can be addressed Control Used to specify the operation requested by the CPU (READ, WRITE, and other handshaking operations) 4

5 0 Memory 5 B n-1 B1B1 0 B0B0 B1B1 1 B0B0 B1B1 2 B0B0 B1B1 M-1 B0B0 n bits (Memory Width) Address (Log 2 M bits) Control Data (n bits)

6 Program Execution Program = Instructions + Data Programs are loaded into memory prior to execution In order to execute the instructions, the CPU Fetches the instruction Read the instruction from memory (Control Unit) Decodes the instruction Understand what should be done (Control Unit) Executes the instruction Perform the required task (Datapath) This is done repeatedly until the end of program ! 6 Fetch Decode Execute

7 The Computer Language Commanding computers requires speaking their language; Binary electric signals at the hardware level (Machine Language) Tedious, time consuming, error-prone, knowledge about processor architecture Make it easier! Represent binary instruction by words (Assembly Language). Convert words to binary manually or using Assemblers Tedious, time consuming, error-prone, knowledge about processor architecture One line corresponds to one instruction!! Make it even easier! Make expressing instructions closer to the way humans express operations (High- level Languages ) Conversion to machine language is done automatically using Compilers 7 Suppose we want to perform two operations 1)Add two numbers X and Y and store the result in Z 2)Assign element 5 from array ARR to W ADD Z, X, Y READW, ARR[5] Z = X + Y W = ARR[5]

8 Instruction Set Architecture Designing processors requires specifying the type and number of instructions the processor is supposed to support and how a programmer can use it This is specified by the instruction set architecture (ISA) of the processor which includes Instructions (type, encoding, operation …) Memory and I/O access Registers (Why do we need registers !) Different processors have different ISA IA-32, MIPS, SPARC, ARM, DEC, HP, IBM, … The same ISA can be implemented in different ways to achieve different goals Single-cycle, multi-cycle, pipelining, … 8

9 Instruction Set Architecture Generally, the design of ISA could follow one of two schools CISC - Complex Instruction Set Computers RISC - Reduced Instruction Set Computers (~1980s ) 9 CISCRISC Many instructions and addressing modes Few instructions and addressing modes Instructions have different levels of complexity (different size and execution time) Simple instructions of fixed size Shorter programsLonger programs Relatively slowRelatively fast Expensive !!! (not really)Cheaper !! (not really) Intel, AMD, Cyrix MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC

10 The MIPS ISA Historical Facts Microprocessor without Interlocked Pipeline Stages First MIPS processor by John Hennessey in 1981 at Stanford University MIPS Technologies, Inc First commercial model R General Features RISC 32-bit and 64-bit Register-Register Architecture ( Load-Store ) ISA revisions  MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64 Different processor models R2000, R3000, R4000, R

11 The MIPS ISA – Register File B 31 B1B1 31 B0B0 32 bits B 31 B1B1 B0B0 B1B1 B0B0 B1B1 B0B0 Read Addr 1 Read Addr 2 Write Addr Write Data Read/Write Read Data 1 Read Data 2 Inside the CPU SRAM !! Hold data temporarily Some sort of caching of data Why two read ports ?

12 #NamePurpose $0$zeroConstant zero $1$atReserved for assembler $2$v0Function return value $3$v1 $4$a0Function parameter $5$a1 $6$a2 $7$a3 $8$t0Temporary – Caller-saved $9$t1 $10$t2 $11$t3 $12$t4 $13$t5 $14$t6 $15$t7 #NamePurpose $16$s0Temporary – Callee-saved $17$s1 $18$s2 $19$s3 $20$s4 $21$s5 $22$s6 $23$s7 $24$t8Temporary – Caller-saved $25$t9 $26$k0Reserved for OS $27$k1 $28$gpGlobal pointer $29$spStack pointer $30$fpFrame pointer $31$raFunction return address The MIPS ISA – Register File When writing assembly, these registers can be referenced by their address (number) or name General purpose and special purpose registers 12

13 The MIPS ISA – Register File There are other registers ! Not directly accessible (no address) PC: Program counter Instruction sequencing LO and HI Used with multiplication and division instructions 13 PC LO HI 32 bits

14 The MIPS ISA - Instructions Different categories Arithmetic, logical, memory, flow control All instructions are encoded in binary using 32 bits (Fixed Size!!!) Three different formats depending on the number and type of operands, and operation R-type I-type J-type Instruction encoding Opcode  operation code that specifies the operation in binary Operands  the ins and outs of the instruction 14

15 Arithmetic instructions The MIPS ISA - Instructions 15 A = B + C F = C - A ADDA, B, C SUBF, C, A ADD$s0, $s1, $s2 #$s0 = $s1 + $s2 SUB$t2, $s6, $s4 #$t2 = $s6 - $s4 OperationDestination, Source1, Source2 destination  source1 op source2 Each arithmetic instruction performs one operation Each instruction has three operands The operands are in the file registers of the datapath The order of operands is fixed

16 Arithmetic instructions The MIPS ISA - Instructions 16 Example 1. Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far. a = b – c d = 3 * a Solution: assume that the variables a, b, c, and d are associated with registers $s0, $s1, $s2, and $s3, respectively, by the compiler. sub $s0, $s1, $s2 # $s0 contains b – c add $s3, $s0,$s0 # $s3 contains 2*a add $s3, $s3, $s0 # $s3 contains 3*a

17 Arithmetic instructions The MIPS ISA - Instructions 17 Example 2. Given the following piece of C code, find the equivalent assembly code using the basic MIPS ISA given so far. f = (g + h) – (i + j) Solution: assume that the variables f, g, h, i, and j are associated with registers $s0, $s1, $s2, $s3, and $s4, respectively, by the compiler. add $t0, $s1, $s2 # $t0 contains g + h add $t1, $s3,$s4 # $t1 contains i + j sub $s0, $t0, $t1 # $s0 contains (g+h) – (i+j) More efficient translation!???

18 The MIPS ISA - Instructions Arithmetic Instructions Machine Language Any instruction has to be encoded using 32 bits including the operation and its operands 18 ADD $t0, $s1, $s4 oprsrtrd shamt funct op 6-bitsopcode that specifies the operation rs 5-bitsregister file address of the first source operand rt 5-bitsregister file address of the second source operand rd 5-bitsregister file address of the result’s destination shamt 5-bitsshift amount (for shift instructions) funct 6-bitsfunction code augmenting the opcode R-type

19 The MIPS ISA - Instructions Arithmetic Instructions Machine Language Example 3. What is the machine code for ADD $s0, $t0, $s4 19 ADD $s0, $t0, $s s B H

20 The MIPS ISA - Instructions Arithmetic Instructions Machine Language Example 4. What is the machine code for SUB $s1, $s2, $s3 20 SUB $s1, $s2, $s s B H

21 The MIPS ISA - Instructions Logical Instructions AND, OR, NOR Operation is performed between corresponding bits (bitwise) R-type instruction format Example 5. What is the machine code for AND $s1, $t2, $s2 op = 0x0 rs = $t2 = 0x0A rt = $s2= 0x12 rd = $s1 = 0x11 shamt = 0x00 funct = 0x24 21 AND $s4, $s3, $t4 # $s4 = $s3 & $t4 OR $s0, $t7, $s3 # $s0 = $t7 | $s3 NOR $s2, $t6, $s3 # $s2 = ~($t6 | $s3) oprsrtrdshamtfunc

22 The MIPS ISA - Instructions 22 Arithmetic and Logic Instructions with Immediate In many occasions, we encounter high-level statements such as X = Y + 5 Z = W – 4 F = 514 x R If (C>-3) … This implies that the operation is between a register and some constant ! Can we do this with ADD and SUB instructions? Where do these constants come from? MIPS ISA specifies a new set of instructions that deal with immediate data ADDI, ORI, ANDI, XORI, …

23 The MIPS ISA - Instructions 23 Arithmetic and Logic Instructions with Immediate ADDI $t5, $s3, 130 ADDIU$s1,$s2, 15 oprsrtImmediate I-type Instruction Register File Sign Extension Reg[rs] Immediate Addressing!

24 The MIPS ISA - Instructions 24 Arithmetic and Logic Instructions with Immediate ANDI $t1, $t3, 12 ORI$s3,$a0, 123 oprsrtImmediate I-type Instruction Register File Zero Extension & Reg[rs] Immediate Addressing!

25 The MIPS ISA - Instructions 25 Arithmetic and Logic Instructions with Immediate What if the immediate is greater than 16 bits? In MIPS, this is achieved in two steps using the Load Upper Immediate (LUI) and ORI instructions Suppose we want to add the constant ( ) 2 to $s0 LUI$t0, # loads the upper 16 bits of $t0 and sets the lower 16 bits to 0 LUI$t0, ( ) 2 ORI$at, $t0, ( ) 2

26 Memory instructions MIPS ISA address bus is 32 bits, i.e. it can address up to 2 32 (4 G) locations Memory width is usually 8 bits (byte) The MIPS ISA - Instructions 26 8 bits 0x x x xFF FF FF FF MIPS CPU 32-bit Address Bus (32 bits) Data Bus (32 bits) Read Write

27 Memory instructions Most memories are byte addressable ! Every four consecutive locations (8 bits each) form a word (32 bits) ! In other words, the addresses of two consecutive locations differ by 4 The MIPS ISA - Instructions 27 8 bits 0x x x x x x x x x x x A 0x B 0x C 0x D 0x E 32 bits 0x x x x C 0x x x x C 0x

28 Memory instructions Reading from memory requires specifying the address to read from and a register to store the read data Writing to memory requires specifying an address to write to and a register whose content will be written to memory Simple ! However, addressing a memory location requires 32 bits Where do these bits come from ?! Are they stored in memory?! Are they part of the instruction ?! Displacement Addressing In MIPS the address is formed by adding the content of some register (the base register) to 16-bit signed constant (offset or displacement) that is part of the instruction itself. The offset is sign-extended to 32 bits to match the size of the register. The MIPS ISA - Instructions 28

29 Memory instructions The Load instruction – reads 32 bit value (A word) into a register The MIPS ISA - Instructions 29 lw $t0, 4 ($s4) OperationDestinationBase RegisterOffset Reg[$t0] = MEM[Reg[$s4]+sign_extend(4)] Register File + Instruction Memory Sign Extension offset Memory Data Register Content Address

30 Memory instructions The Store instruction – writes the 32 bits (A word) found in a register into a memory location The MIPS ISA - Instructions 30 sw $t5, -12 ($t1) NemunicDestinationBase RegisterOffset MEM[Reg[$t1]+sign_extend(-12)] = Reg[$t5] Register File + Instruction Memory Sign Extension offset Register Content Address

31 Memory instructions The memory is byte-addressable. However, the load and store instructions deal with words (4 bytes)! Reading from memory is effectively reading four bytes! How these bytes are ordered in the 32 bit register ? Storing to memory is storing 32 bits in four consecutive locations. What is the order by which these bits are stored in 4 different locations? Two approaches Little endian: the least significant byte is associated with the location of lowest address (Intel) Big endian: the most significant byte is associated with the lowest address (MIPS) The MIPS ISA - Instructions 31

32 Reading a word from memory The MIPS ISA - Instructions 32 0x10 0x33 0x43 0xFD 0x F2 0x F3 0x F4 0x F5 8 bits Memory 0x100x330x430xFD Register Little Endian 32 bits 0x100x330x430xFD Register Big Endian 32 bits Byte 0Byte 1Byte 2Byte 3 Byte 0Byte 1Byte 2Byte 3

33 Memory Instructions Example 7. Convert the following high-level statements to MIPS assembly language G = 2 * F A[17] = A[16] + G Solution assume that the variables F and G are associated with registers $s4 and $s5, respectively, and the base address of the array A is in $s0. All values are 32-bit integers. add $s5, $s4, $s4 # $s5 contains 2*F lw $t0, 64($s0) # $t0 contains A[16] (note the offset is 64) add $t0, $t0, $s5 # $t0 contains A[16] + G sw $t0, 68($s0) # store $t0 in A[17] (note the offset is 68) The MIPS ISA - Instructions 33

34 The MIPS ISA - Instructions Memory Instructions - Machine Language 34 lw $t0, 4 ($s4) sw $t2, -6 ($at) oprsrtOffset (displacement) op 6-bitsopcode that specifies the operation rs 5-bitsregister file address containing the base address rt 5-bitsregister file address of destination register (LW) or the source register (SW) Offset 16-bitsdisplacement or offset (number of bytes to move, positive or negative) I-type How far can we move in memory when using LW and SW?

35 Memory Instructions Example 6 The MIPS ISA - Instructions 35 Machine code for lw $s5, 4($s1) in hexadecimal op = 0x23 rs = $s1 = 0x11 rt = $s5 = 0x15 offset = 0x0004 Machine code for sw $s0, 16($s4) in hexadecimal op = 0x2b rs = $s4 = 0x14 rt = $s0 = 0x10 offset = 0x bits5 bits 16 bits OpcodersrtOffset

36 Memory Instructions MIPS ISA defines memory instructions that can load/store bytes (8 bits) and half words (16 bits) lb $t0, 1($s3) #load byte from memory (sign extention) lbu $t0, 1($s3) # load byte from memory (zeros extension) sb $t0, 6($s3) #store byte to memory lh $t0, 1($s3) #load half word from memory (sign extension) lhu $t0, 1($s3) #load half word from memory (sign extension) sh $t0, 6($s3) #store half word to memory When loading a byte into 32-bit register, where is it stored? Lower 8 bits of the register ! What about remaining bits? When loading a half word into 32-bit register, where is it stored? Lower 16 bits of the register ! What about remaining bits? How about sb and sh instructions? The MIPS ISA - Instructions 36

37 Memory Instructions The MIPS ISA - Instructions 37 0xD0 0xC3 0x43 0xFD 0x F2 0x F3 0x F4 0x F5 8 bits Memory 0x00 0xD0 $s0 32 bits Byte 0Byte 1Byte 2Byte 3 LBU$s0, 2 ($s4) # assume Reg[$s4] = 0x F0 0xFF 0xD0 $s0 32 bits Byte 0Byte 1Byte 2Byte 3 LB$s0, 2 ($s4) # assume Reg[$s4] = 0x F0 0x30 0x04 0x F0 0x F1 What if the instructions are LH and LHU?

38 Flow Control Instructions Instructions are loaded in memory! The normal execution of programs is sequential; one instruction after another! Keeping track of execution is done through a special register called the Program Counter (PC) 32 bits (Why???) It is incremented automatically by 4 (why!) after an instruction is fetched Thus, its contents always holds the address of the next instruction! It is not directly accessible !!! (Why) However, in our programs, we often write statements that skip some parts of the program, conditionally or unconditionally !! (IF, SWITCH, WHILE, GOTO … ) How is this implemented in the hardware !? The MIPS ISA - Instructions 38

39 Flow Control Instructions How to skip instructions in memory to execute others? Basically, this requires using instructions that change the contents of the PC to point to the address where the target instructions are loaded (branch/jump address)! In MIPS, there are no instructions that can modify the PC directly! Alternatively, we have two conditional and three unconditional flow control instructions! These instructions can change the contents of the PC indirectly! The MIPS ISA - Instructions 39

40 Conditional Flow Control Instructions Branch If Equal Instruction (BEQ) Checks if two registers are equal! If true, then the PC (containing the address of next instruction) is incremented or decremented by adding a signed 16-bit offset (that is part of the instruction) after it is multiplied by 4 (WHY?). If false, program execution continues normally from the address in PC. This is called PC-relative addressing! The MIPS ISA - Instructions 40 BEQ $t0, $t1, 15 Operation Tested RegistersOffset

41 Conditional Flow Control Instructions Branch If Equal Instruction (BEQ) The MIPS ISA - Instructions 41 PC Reg1Reg2 Instruction =? x4 MUXMUX Sign Extension + Address of instruction following BEQ Branch Address BEQ …. MEM …. 16 bit offset 32 bit instruction from branch address (two registers are equal) 32 bit instruction next to BEQ (Two registers are not equal)

42 Conditional Flow Control Instructions Branch If Not Equal Instruction (BNE) Checks if two registers are not equal! If true, then the PC (containing the address of next instruction) is incremented or decremented by adding a signed 16-bit offset (that is part of the instruction) after it is multiplied by 4 (WHY?)). If false, program execution continues normally from the address in PC. This is called PC-relative addressing! The MIPS ISA - Instructions 42 BNE $t0, $t1, -23 Operation Tested RegistersOffset

43 Flow Control Instructions (Conditional) Branch If Not Equal Instruction (BNE) The MIPS ISA - Instructions 43 PC Reg1Reg2 Instruction =? x4 MUXMUX Sign Extension + Address of instruction following BNE Branch Address BNE …. MEM …. 16 bit offset32 bit instruction from branch address (Two registers are not equal) 32 bit instruction next to BNE (Two registers are equal)

44 Flow Control Instructions Example 8. Convert the following high-level statements to MIPS assembly language if (x == y) x = x + y end The MIPS ISA - Instructions 44 Solution assume that the variables x and y are associated with registers $s4 and $s5, respectively. BNE$s4, $s5, 1 # if $s5 ~= $s4, skip one instruction ADD$s4, $s4, $s5 # add x and y if they are equal … OR, we can use labels instead of counting how many instructions to skip! BNE$s4, $s5, SKIP # if $s5 ~= $s4, skip one instruction ADD$s4, $s4, $s5 # add x and y if they are equal SKIP: ….

45 The MIPS ISA - Instructions Flow Control Instructions -Machine Language 45 BEQ $t0, $t1, 4 BNE $t2, $v1, -214 oprsrtOffset (displacement) op 6-bitsopcode that specifies the operation rs 5-bitsfirst register file address to be compared rt 5-bitssecond register file address to be compared Offset 16-bitsdisplacement or offset (number of instructions to skip, positive or negative!) I-type How many instructions can we skip when using BNE and BEQ?

46 Conditional Flow Control Instructions Example 9. Machine code for BEQ $s5, $s1, 20 in hexadecimal. op = 0x04 rs = $s5 = 0x15 rt = $s1 = 0x11 offset = 0x0014 Machine code for BNE $s0, $s1, -13 in hexadecimal op = 0x05 rs = $s0 = 0x10 rt = $s1 = 0x11 offset = 0xFFFD The MIPS ISA - Instructions

47 Conditional Flow Control Instructions BEQ and BNE instructions can check for equality only? How about >, = ??? There are no instructions such bgt, bls, bge, ble!! In MIPS ISA, this can be done with the aid of The Set On Less than Instructions (SLT and SLTU) Compares if one register is less than another one If so, a third register is loaded with 1 Otherwise, the third register is loaded with 0 The $Zero register Register number zero Hardwired to zero Can be read only! The MIPS ISA - Instructions 47

48 Conditional Flow Control Instructions SLT Instruction The MIPS ISA - Instructions 48 SLT$s1, $s2, $s3#set $s1 if $s2 < $s3, else clear $s1 $S2 $S3 - $s2-$s3<0 ?? $S1 = 1 $S1 = 0 Yes No

49 The MIPS ISA - Instructions 49 SLT $t0, $s1, $s4 oprsrtrd shamt funct Opcode for SLT is 0x00 and the func field is 0x2a How about comparing with constants? SLTI How about comparing unsigned numbers? SLTU and SLTIU R-type Conditional Flow Control Instructions SLT Instruction – Machine Language

50 Conditional Flow Control Instructions So, how can we execute blt$s1, $s2, L1 ? Such instructions are included in the ISA as pseudo instructions (fake). The assembler takes the job of converting them to actual assembly instructions through using the $at register How about other branch instructions? The MIPS ISA - Instructions 50 slt$at, $s1, $s2 bne$at, $zero, L1 ………. L1: blt$s1, $s2, L1 ………. L1:

51 Unconditional Flow Control Instructions Occasionally, we might need to skip part of the program unconditionally! In MIPS, this is achieved by jump instruction which loads the PC with the 32-bit address of the jump location The 32-bit jump address is formed by Extracting the upper four bits of the PC (Address of next instruction) Appending them to a 26-bit number found in the instruction after multiplying it by 4 (WHY!!!) This is called Pseudo-direct Addressing The MIPS ISA - Instructions 51 J label #go to label

52 Unconditional Flow Control Instructions The Jump Instruction The MIPS ISA - Instructions 52 PC Instruction Address Field Shift left by 2 = 26 bits 28 bits 4 bits32 bits

53 Unconditional Flow Control Instructions The Jump Instruction – Machine Language Opcode 0x02 How far can we move using the jump instruction? What is the machine code for j 136 ? What is the jump addres if the address of the instruction is 0x ? The MIPS ISA - Instructions 53 JLabel opAddress Field 6 26 J-type

54 Branching Far Away ! In programs, branches are local usually! What if we need to skip more than or instructions ! The assembler utilizes the Jump instruction and inverts the condition The MIPS ISA - Instructions 54 beq$s0, $s1, L1 ………. L1: bne$s0, $s1, L2 jL1 L2: ………… ………… L1:

55 High-level languages support procedures/functions Modularity and code reuse ! Calling a procedure requires Changing the program flow to the place where the procedure is located in memory (branching!!!) Passing arguments ! Storing return values! Returning to the calling program! How is this implemented in the MIPS ISA? The MIPS ISA - Instructions 55 Instructions for Accessing Procedures Program Procedure Memory

56 The Jump and Link (JAL) instruction! This instruction loads the PC with the 32-bit address of the procedure The procedure address is formed in the same way the jump address is formed in the Jump instruction (Pseudo Addressing) Additionally, the instruction saves the contents of the PC in the Return Address register ( $ra ) ! (WHY!!) The MIPS ISA - Instructions 56 Instructions for Accessing Procedures JAL ProcedureX Operation Part of the procedure address (26 bits from the instruction)

57 The Jump Register (JR) instruction! When the execution of the procedure is finished, it is assumed that the CPU should go back to where it was before invoking the procedure This is done by using the JR instruction Basically, the instruction loads the PC with the contents of some register! In procedures, this register is $ra The MIPS ISA - Instructions 57 Instructions for Accessing Procedures JR $t0# Return oprsrtrd shamt funct R-type

58 How to pass procedure arguments ? The argument registers ! Registers $a0, $a1, $a2, and $a3 Where to store return values ? The value registers ! Registers $v0 and $v1 What if the procedure uses registers in the caller? What if the procedure calls another one? Temporarily save these registers in memory during procedure execution Retrieve these values upon procedure completion! The STACK ! The MIPS ISA - Instructions 58 Instructions for Accessing Procedures

59 The Stack An area of memory used for temporary storage It is a last-in-first out queue Can be accessed like other memory location using Load and Store instructions! However, the base register is a special register called the Stack Pointer ($SP) By convention, the stack grows from high to low address! (WHY!) The SP always points to an occupied location (Top of Stack) Two basic operations on Stack Saving (PUSH)  write data to stack Reading (POP)  read data from stack The MIPS ISA - Instructions 59 Instructions for Accessing Procedures

60 The Stack Push Operation Pop Operation The MIPS ISA - Instructions 60 Instructions for Accessing Procedures High Address Low Address 1)$sp = $sp – 4 2)Store data (word) starting at location pointed by SP! SP New SP 1)Read data (word) starting at location pointed by SP! 2)SP = SP + 4 High Address Low Address SP New SP WW XX YY ZZ WW XX YY ZZ

61 Example 10. Convert the following code fragment to MIPS assembly (Leaf Procedure) int func1 (int g, h) { int f ; f = (g + h) ; return f ; } Assumptions Argument variables g and h are in argument registers $a0 and $a1, respectively f is assigned to $s0 (need to be saved in stack!) Return value in $v0 The MIPS ISA - Instructions 61 Instructions for Accessing Procedures

62 Example 10. func1:addi$sp, $sp, -4 sw$s0, 0($sp) add$s0, $a0, $a1 add$v0, $s0, $zero lw$s0, 0($sp) addi$sp, $sp, 4 jr$ra The MIPS ISA - Instructions 62 Instructions for Accessing Procedures Push $s0 to stack The procedure Put return value in $v0 Pop $s0 from stack Return

63 MIPS Design Principles 63 1) Simplicity favors regularity Fixed instruction size Few instruction formats Opcode is the first 6 bits 2) Good design demands good compromise Three instruction formats 3) Smaller is faster Limited instruction set Small register file Few addressing modes 4) Make the common case fast Operands are from register file Instructions contain immediate data

64 Non-leaf procedures Example in section 2.8 Translating and Starting a Program Section 2.12 The Intel x86 ISA Section 2.17 Further Reading 64

65 Processor Memory 32 bits 2 30 words read/write addr read data write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 registers ($zero - $ra) PC ALU byte address (big Endian) Fetch PC = PC+4 DecodeExecute Add 32 4 Add 32 branch offset MIPS Organization So Far

66 Register addressing – operand is in a register Base (displacement) addressing – operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction Register relative (indirect) with 0($a0) Pseudo-direct with addr($zero) Immediate addressing – operand is a 16-bit constant contained within the instruction Review of MIPS Addressing Modes op rs rt rd funct Register word operand base register op rs rt offset Memory word or byte operand op rs rt operand

67 PC-relative addressing –instruction address is the sum of the PC and a 16-bit constant contained within the instruction Pseudo-direct addressing – instruction address is the 26- bit constant contained within the instruction concatenated with the upper 4 bits of the PC op rs rt offset Program Counter (PC) Memory branch destination instruction op jump address Program Counter (PC) Memory jump destination instruction Review of MIPS Addressing Modes =

68 Powerful instruction  higher performance Fewer instructions required in programming?!?!? But complex instructions are hard to implement! May slow down all instructions, including simple ones Compilers are good at making fast code from simple instructions Use assembly code for high performance But modern compilers are better at dealing with modern processors More lines of code  more errors and less productivity Fallacies 68

69 Sequential words are not at sequential addresses Increment by 4, not by 1 since instructions are 32 bits and memory is word addressable! The offset in branch instructions is the number of instructions It is multiplied in hardware by 4 to convert it to bytes Pitfalls 69

70 Assignment 1. Load-store (register-register) is not the only ISA ! Other ISAs are also available Accumulator Stack Register-Memory Memory-Memory Search the web and read more about these ISAs Assignment 2. Read Section 2.17 – Real Stuff : x86 Instructions Reading Assignment 70

71 Example 11. Convert the following high-level code into MIPS assembly language. Make your own association for registers. Assume array to contain signed 32-bit values. A = 5 ; B = 2 * A ; if B < array[12] then array[12] = 0 else array[12] = -20 end More Examples 71

72 Example 12. Assume that the following assembly code is loaded in memory. Draw the memory and show its contents assuming that the program counter starts at 0x add $s0, $s1, $s2 beq $s0, $s3, Next lw $s0, -15($s5) Next: lw $s0, 5($s6) More Examples 72

73 Example 13. W hat is the assembly language instruction that corresponds to each of the following machine codes 0x00af8020 0x0c More Examples 73

74 Example 14. The address of the instruction being executed is 0x , then If this instruction is add $s0, $t9, $zero, then what is the address of the instruction executed after this instruction ? If this instruction is j 256, then what is the address of the instruction executed after this instruction? If this instruction is jal 100, then what is the content of the $ra register after executing this instruction? If this instruction is beq $s1, $s2, 25 and the condition evaluates to true, then what is the address of the instruction executed after this instruction ? More Examples 74

75 Example 15. Convert the following high-level statements into MIPS assembly language. intx ; 32-bit signed number short unsigned int Array[32] ; 16-bit unsigned for (x=0; x=31; x++) { Array[x] = 2 * Array[x] ; } More Examples 75

76 Example 16. Convert the following function into MIPS assembly language. Assume that the variable i is in $s0. void strcpy (char x[ ], char y[ ]) { int i; i = 0 ; while ((x[i] = y[i]) != ‘\0’) i += 1 ; } More Examples 76


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