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ENGG3190 Logic Synthesis “Sequential Circuit Synthesis” Winter 2014 S. Areibi School of Engineering University of Guelph

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Outline Modeling Modeling synchronous circuits – State-based models. – Structural models. optimization State-based optimization methods – Stateminimization – State minimization. completely specified State minimization for completely specified machines incompletely specified State minimization for incompletely specified machines. – State encoding State encoding for two-level logic State encoding for two-level logic State encoding for multiple-level logic State encoding for multiple-level logic Structural-based optimization methods Structural-based optimization methods – Retiming 2

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3 Combinational vs. Sequential Circuits 1.Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer. Combinational circuits cannot remember what happened in the past (i.e. outputs are a function of current inputs). 2.In certain cases we might need to store some info before we proceed with our computation or take action based on a certain state that happened in the past. Sequential circuits are capable of storing information between operations. They are useful in designing registers, counters, and CONTROL Circuits, …

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4 Types of Sequential Circuits Two main types and their classification depends on the times at which their inputs are observed and their internal state changes. Synchronous: State changes synchronized by one or more clocks Asynchronous: Changes occur independently

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What are Sequential Circuits? Some Some sequential circuits have memory elements. clocked – Synchronous circuits have clocked latches. not clocked – Asynchronous circuits may or may not have latches (e.g. C-elements), but these are not clocked. necessary Feedback (cyclic) is a necessary, but not sufficient condition for a circuit to be sequential. not (only small circuits) Synthesis of sequential circuits is not as well developed as combinational. (only small circuits) not really used (except maybe retiming). Sequential synthesis techniques are not really used in commercial software (except maybe retiming). verification Sequential verification is a problem.

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6 Synchronous/Asynchronous Analog Asynchronous Synchronous Time Continuous in value & time Discrete in value & continuous in time Discrete in value & time Digital

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7 Comparison Synchronous Easier to analyze because can factor out gate delays Speed of the system is determined by the clock (maybe slowed!) Asynchronous Potentially faster Harder to analyze We will only look at Synchronous Circuits

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Example state The above circuit is sequential since primary output depends on the state and primary inputs. Latch Present State Next State in1 in2 in3 in4 out 1 primary inputs primary output 0 1 ---1/1 ----/1 (--00, 11-0)/0 (1010, 0110)/1 Registers and Latches (Netlist) State Transition Graph (STG)

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9 Analysis of Sequential Circuits The behavior of a sequential circuit is determined from: Inputs, Outputs, Present state of the circuit. The analysis of a sequential circuit consists of: Obtaining a suitable description that demonstrates the time sequence of inputs, outputs and states (STATE DIAGRAM).

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10 Derive Input Equations Can describe inputs to FF with logic equations

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11 State Table Similar to truth table with state added A sequential circuit with `m’ FFs and `n’ inputs needs 2 m+n rows in state table.

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12 State Diagram An alternative representation to State Table Input/Output Input Output “Mealy Model”

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13 State Diagram: Moore Alternative representation for state table State/Output Inputs

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14 Sequential Circuit Types Moore model Moore model – outputs depend on states only. Mealy model Mealy model – outputs depend on inputs & states

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15 Moore vs. Mealy Machine Moore Machine: Easy to understand and easy to code. Might requires more states (thus more hardware). Mealy Machine: They are more general than Moore Machines More complex since outputs are a function of both the state and input. Requires less states in most cases, therefore less components. Choice of a model depends on the application and personal preference. You can transform a Mealy Machine to a Moore Machine and vice versa.

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16 Design Procedure Design starts from a specification and results in a logic diagram or a list of Boolean functions. The steps to be followed are: 1.Derive a state diagram 2.Reduce the number of states (Optimization) 3.Assign binary values to the states (encoding) (Optimization) 4.Obtain the binary coded state table 5.Choose the type of flip flops to be used 6.Derive the simplified flip flop input equations and output equations 7.Draw the logic diagram

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17 Present StateNext State CBAC+B+A+ 000xxx 001xxx 010101 011110 100010 101011 110100 111xxx note the don't care conditions that arise from the unused state codes Synthesis Example Implement simple count sequence Implement simple count sequence: 000, 010, 011, 101, 110 Derive the state transition table from the state transition diagram 101 010100 110 011

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18 C B A X110X1X0X110X1X0 C+C+ C B A X001X1X1X001X1X1 B+B+ C B A X100X0X1X100X0X1 A+A+ C + = B B + = A + B’ C A + = A’ C’ + AC Don’t cares in FSMs (cont’d) Synthesize logic for next state functions derive input equations for flip-flops Some states are not reachable!! Since they are don’t cares. Can we fix this problem?

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19 Self-starting FSMs Deriving state transition table from don't care assignment C B A 0110011001100110 C+C+ C B A 1001111110011111 B+B+ C B A 1100001111000011 A+A+ Present StateNext State CBAC+B+A+ 000011 001010 010101 011110 100010 101011 110100 11111x

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20 Self-starting FSMs Start-up states – at power-up, FSM may be in an used or invalid state – design must guarantee that it (eventually) enters a valid state Self-starting solution – design FSM so that all the invalid states eventually transition to a valid state may limit exploitation of don't cares 101 010100 110 011 000 001 111

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Modeling Synchronous Circuits State-based State-based model – Model – Model circuits as finite-state machines. – Represented by – Represented by state tables/diagrams. – Lacks – Lacks a direct relation between state manipulation and corresponding area and delay variations. – You can Applyexact/heuristic algorithms – You can Apply exact/heuristic algorithms for State minimization. State encoding. Structuralbased Structural-based models synchronouslogic network – Represent circuit by synchronous logic network. – You can Apply Retiming. Logic transformations (recall Multi Level Synthesis Transformations!!) State transition diagrams can be: State transition diagrams can be: – Transformed into synchronous logic networks by state encoding. – Recovered from synchronous logic networks by state extraction. 21

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22 General Logic Structure Combinational optimization –keep latches/registers at current positions, keep their function –optimize combinational logic in between Sequential optimization –change latch position/function (retiming) Combinational logic (CL) Sequential elements

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Overview of FSM Optimization Specification State Minimization State Encoding Logic/Timing Optimization Verification/Testing

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State-Based Models: Optimization 24

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Overview of FSM Optimization Initial: Initial: FSM description 1.provided 1.provided by the designer as a state table 2.extracted 2.extracted from netlist 3.derived 3.derived from HDL description obtained as a by-product of high-level synthesis translate to netlist, extract from netlist State minimizationequivalent not always true State minimization: Combine equivalent states to reduce the number of states. For most cases, minimizing the states results in smaller logic, though this is not always true. State assignmentbinary State assignment: Assign a unique binary code to each state. The logic structure depends on the assignment, thus this should be done optimally. Minimization of a node: Minimization of a node: in an FSM network Decomposition/factoring: Decomposition/factoring: of FSMs, collapsing/elimination Sequential redundancy removal: Sequential redundancy removal: using ATPG techniques

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Formal Finite-State Machine Model S Defined by the quintuple ( , , S, , ). inputs A set of primary inputs patterns . outputs A set of primary outputs patterns . set of states S A set of states S. state transition A state transition function – SS – : S S. output function An output function – S – : S for Mealy models – S – : S for Moore models. 26

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State Minimization Definition: Derive a FSM with similar behavior and minimum number of states. Definition: Derive a FSM with similar behavior and minimum number of states. – Aims at reducing the number of machine states – reduces the size of transition table. may reduce State reduction may reduce? number storage elements – the number of storage elements. combinational logic – the combinational logic due to reduction in transitions Types: Types: 1.Completely specified finite-state machines No don't care conditions. Easy to solve. 2.Incompletely specified 2.Incompletely specified finite-state machines Unspecified transitions and/or outputs Unspecified transitions and/or outputs. Intractable problem. 27

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Redundant States: Minimization 28 S1S1 S4S4 S2S2 S3S3 1/1 1/0 0/0 1/1 0/0 1/1 0/0 Can you distinguish between State S 1 and S 2 ? equivalentStates S 1, S 2 seem to be equivalent! Hence we can reduce the machine accordingly S1S1 S4S4 S3S3 1/1 1/0 0/0 1/1 0/0

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State Minimization for Completely-Specified FSMs Def: Equivalent states match – Given any input sequence the corresponding output sequences match. Theorem: Two states are equivalent iff identical outputs I.they lead to identical outputs and next-statesequivalent II.their next-states are equivalent. Since equivalence is symmetric and transitive partitionedclasses – States can be partitioned into equivalence classes. – Such a partition is unique. 29

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Equivalent States Two states of an FSM are: equivalent – equivalent (or indistinguishable) – if for each input they produce the same output and their next states are identical. 30 Si Sj Sm Sn 1/0 0/0 Si,j Sm Sn 1/0 0/0 Si and Sj are equivalent and merged into a single state.

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Algorithmic State Minimization Goal – identify and combine states that have equivalent behavior smallerfasterless power – Reduced machine is smaller, faster, consumes less power. Algorithm Sketch 1. Place all states in one set 2. Initially partition set based on output behavior 3. Successively partition resulting subsets based on next state transitions 4. Repeat (3) until no further partitioning is required states left in the same set are equivalent Polynomial time procedure

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Equivalent States … Cont Example: States A... I, Inputs I1, I2, Output, Z 32 Present state Next state, output (Z) Input I1 I2 AD / 0C / 1 BE / 1A / 1 CH / 1D / 1 DD / 0C / 1 EB / 0G / 1 FH / 1D /1 GA / 0F / 1 HC / 0A / 1 IG / 1H / 1 A and D are equivalent A and E produce same output Q: Can they be equivalent? A: Yes, if B and D were equivalent and C and G were equivalent.

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Minimization Algorithm Stepwise partition refinement. Let i, i= 1, 2, …., n denote the partitions. Initially belong to the same block – 1 = States belong to the same block when outputs are the same for any input. Refine Refine partition blocks: While further splitting is possible and their next-states – k+1 = States belong to the same block if they were previously in the same block and their next-states are in the same block of k for any input. At convergence i+1 = i – Blocks identify equivalent states. 33

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Example … 1 = {(s1, s2), (s3, s4), (s5)}. Split s3, s4 2 = {(s1, s2), (s3), (s4), (s5)}. 2 = is a partition into equivalence classes – States (s1, s2) are equivalent. 34

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… Cont.. Example … Original FSM Minimal FSM 35

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… Example {OUT_0} = IN_0 LatchOut_v1' + IN_0 LatchOut_v3' + IN_0' LatchOut_v2' v4.0 = IN_0 LatchOut_v1' + LatchOut_v1' LatchOut_v2' v4.1 = IN_0' LatchOut_v2 LatchOut_v3 + IN_0' LatchOut_v2' v4.2 = IN_0 LatchOut_v1' + IN_0' LatchOut_v1 + IN_0' LatchOut_v2 LatchOut_v3 sis> print_stats pi= 1 po= 1 nodes= 4 latches= 3 lits(sop)= 22 #states(STG)= 5 {OUT_0} = IN_0 LatchOut_v1' + IN_0 LatchOut_v2 + IN_0' LatchOut_v2' v3.0 = IN_0 LatchOut_v1' + LatchOut_v1' LatchOut_v2‘ v3.1 = IN_0' LatchOut_v1' + IN_0' LatchOut_v2' sis> print_stats pi= 1 po= 1 nodes= 3 latches= 2 lits(sop)= 14 #states(STG)= 4 Original FSM Minimal FSM 36

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Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1S200 0S1S3S400 1S2S5S600 00S3S0S000 01S4S0S010 10S5S0S000 11S6S0S010 State Minimization Example Sequence Detector for 010 or 110 S0 S3 S2S1 S5S6S4 1/00/0 1/0 0/1 0/01/00/0 1/0 0/0 1/0 0/1 1/0 0/0

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( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 ) ( S0 S1 S2 ) ( S3 S5 ) ( S4 S6 ) ( S0 ) ( S1 S2 ) ( S3 S5 ) ( S4 S6 ) Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1S200 0S1S3S400 1S2S5S600 00S3S0S000 01S4S0S010 10S5S0S000 11S6S0S010 S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6 Method of Successive Partitions

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Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1'S1'00 0 + 1S1'S3'S4'00 X0S3'S0S000 X1S4'S0S010 Minimized FSM State minimized sequence detector for 010 or 110 S0 S1’ S3’ S4’ X/0 1/0 0/1 0/0 X/0

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Computational Complexity Polynomially-bound algorithm. There can be at most |S| partition refinements. Each refinement requires considering each state – Complexity O(|S| 2 ). Actual time may depend upon – Data-structures. – Implementation details. 40

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Implication Table Method 41 A B CD E FG H BCDEFGHI EG AH Present state Next state, output (Z) Input I1 I2 AD / 0C / 1 BE / 1A / 1 CH / 1D / 1 DD / 0C / 1 EB / 0G / 1 FH / 1D / 1 GA / 0F /1 HC / 0A / 1 IG / 1H / 1 GH DH GH DH √ BD CG AD CF √ CD AC EH AD EH AD CF CD AC BC AG BD CG AC AF AB FG

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Implication Table Method (Cont.) 42 A B CD E FG H BCDEFGHIBCDEFGHI √ BD CG AD CF √ CD AC EH AD EH AD EG AH AD CF CD AC BC AG BD CG AC AF GH DH GH DH Equivalent states: S1:A, D, G S2:B, C, F S3:E, H S4:I AB FG

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Minimized State Table 43 Present state Next state, output (Z) Input I1 I2 AD / 0C / 1 BE / 1A / 1 CH / 1D / 1 DD / 0C / 1 EB / 0G / 1 FH / 1D / 1 GA / 0F / 1 HC / 0A / 1 IG / 1H / 1 Present state Next state, output (Z) Input I1 I2 S1 = (A, D, G)S1 / 0S2 / 1 S2 = (B, C, F)S3 / 1S1 / 1 S3 = (E, H)S2 / 0S1 / 1 S4 = IS1 / 1S3 / 1 OriginalMinimized Number of flip-flops is reduced from 4 to 2.

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Incompletely Specified Machines don’t cares Next state and output functions have don’t cares. functions However, for an implementation, and are functions, – thus they are uniquely defined for each input and state combination. Don’t cares arise when some combinations are of no interest: not occur – they will not occur or not be observed – their outputs will not be observed For these, the next state or output may not be specified. relations – (In this case, and are relations, but of special type. We should make sure we want these as don’t cares.) incompletely specified Such machines are called incompletely specified.

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… State Minimization for Incompletely Specified FSMs Minimum finite-state machine is not unique. Implication relations make problem intractable. Example – Replace * by 1. {(s1, s2), (s3), (s4), (s5)}. 45 Minimized to 4 states

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… State Minimization for Incompletely Specified FSMs Minimum finite-state machine is not unique. Example – Replace * by 0. {(s1, s5), (s2, s3, s4)}. 46 0 0 It is now completely specified Unfortunately, there is an exponential number of completely specified FSMs in correspondence to the choice of the don’t care values!!

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Example dummy By adding a dummy state this can be converted to a machine with only the output incompletely specified. “error” Could also specify “error” as the output when transitioning to the dummy state. (better for optimization), Alternatively (better for optimization), can interpret undefined next state as allowing any next state. s1s1 s2s2 1/1 1/- 0/0 s1s1 s2s2 1/1 1/- 0/0 0/- s1s1 s2s2 1/1 1/- 0/0 d 0/- -/- added dummy non-acceptingstate added transitions to all states and output any value

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48 State Encoding Binary and Gray encoding use the minimum number of bits for state register Gray and Johnson code: Gray and Johnson code: – Two adjacent codes differ by only one bit Reduce simultaneous switching Reduce simultaneous switching – Reduce crosstalk – Reduce glitch #BinaryGrayJohnsonOne-hot 0000 000000000001 1001 000100000010 2010011001100000100 3011010011100001000 4100110111100010000 5101111111000100000 6110101110001000000 7111100100010000000

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49 State Encoding The cost & delay of FSM implementation depends on encoding of symbolic states. – e.g., 4 states can be encoded in 4! = 24 different ways There are more than n! different encodings for n states. – exploration of all encodings is impossible, therefore heuristics are used Heuristics Used: 1.One-hot encoding 2.minimum-bit change 3.prioritized adjacency

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50 One-hot Encoding Uses redundant encoding in which one flip-flop is assigned to each state. Each state is distinguishable by its own flip-flop having a value of 1 while all others have a value of 0. ABC S = 0 S = 1 Z = 0 Z = 1 A 00 S 01 B C 01 10 Z 01

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51 Minimum-bit Change bit changes is minimized Assigns codes to states so that the total number of bit changes for all state transitions is minimized. number of bits differminimizes the sum In other words, if every arc in the state diagram has a weight that is equal to the number of bits by which the source and destination encoding differ, this strategy would select the one that minimizes the sum of all these weights. Encoding with 6 bit changes Encoding with 4 bit changes

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111 111 111 11 The Idea of Adjacency Inputs are A and B State variables are Y1 and Y2 An output is F(A, B, Y1, Y2) A next state function is G(A, B, Y1, Y2) 52 A B Y1 Y2 Karnaugh map of output function or next state function Larger clusters produce smaller logic function. Clustered minterms differ in one variable.

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Size of an Implementation product terms Number of product terms determines number of gates. literals inputs Number of literals in a product term determines number of gate inputs, which is proportional to number of transistors. Hardware α (total number of literals) Examples of four minterm functions: F1 = ABCD + A B C D + A BCD + AB CD has 16 literals F2 = ABC + A CD has 6 literals 53

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Rule 1 (Priority #1), Common Dest same next state adjacent codes States that have the same next state for some fixed input should be assigned logically adjacent codes. 54 Combinational logic Flip- flops Outputs Fixed Inputs Present state Next state Clock Clear Si Sj Sk Rule #1: (S 1, S 2 ) The input value of 0 will move both states into the same state S 3 S0S0 S3S3 S2S2 S1S1 0/0 0/1 0/0 1/0 0/1, 1/1

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Rule 2 (Priority #2), A Common Source Statesare the next states the same state adjacent codes States that are the next states of the same state under logically adjacent inputs, should be assigned logically adjacent codes. 55 Combinational logic Flip- flops Outputs Adjacent Inputs Fixed present state Next state Clock Clear Sk Sm Si I1 I2 S0S0 S3S3 S2S2 S1S1 0/0 0/1 0/0 1/0 0/1, 1/1 Rule #2: (S 1, S 2 ) They are both next states of the state S 0

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Rule 3 (Priority #3), A Common Output Stateshave the same output value the same input valueadjacent codes States that have the same output value for the same input value, should be assigned logically adjacent codes. 56 Combinational logic Flip- flops Outputs Adjacent Inputs Fixed present state Next state Clock Clear Sk Sm Si I1 I2 S0S0 S3S3 S2S2 S1S1 0/0 0/1 0/0 1/0 0/1, 1/1 01 0010 11 0/0 0/1 0/0 1/0 0/1, 1/1 Rule #3: (S 0, S 1 ), and (S 2, S 3 ), states S 0 and S 1 have the same output value 0 for the same input value 0

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Example of State Assignment 57 Present state Next state, output (Z) Input, X 0 1 AC, 0D, 0 BC, 0A, 0 CB, 0D, 0 DA, 1B, 1 DB A C 0/0 1/0 1/1 0/1 A adj B (Rule 1) A adj C (Rule 1) B adj D (Rule 2) C adj D (Rule 2) AB CD 0 1 0101 Verify that BC and AD are not adjacent.

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State Assignment #1 58 Present state Y1, Y2 Next state, output Y1*Y2*, Z Input, X 0 1 A = 0010 / 011 / 0 B = 0110 / 000 / 0 C = 1001 / 011 / 0 D = 1100 / 101 / 1 InputPresent state OutputNext state XY1Y2ZY1*Y2* 000010 001010 010001 011100 100011 101000 110011 111110 A = 00, B = 01, C = 10, D = 11

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Logic Minimization for Optimum State Assignment 59 111 11 Y2 X Y1 111 Y2 Y1 11 Y2 X Y1 X Z Y1* Y2* Result: 5 products, 10 literals.

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Circuit for Optimum State Assignment 60 Y2 Y1 Y1 Y2 X Z Y2* Y1* CK CLEAR Combinational logic 32 transistors

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Using an Arbitrary State Assignment: A = 00, B = 01, C = 11, D = 10 61 Present state Y1, Y2 Next state, output Y1*Y2*, Z Input, X 0 1 A = 0011 / 010 / 0 B = 0111 / 000 / 0 C = 1101 / 010 / 0 D = 1000 / 101 / 1 InputPresent state OutputNext state XY1Y2ZY1*Y2* 000011 001011 010100 011001 100010 101000 110101 111010

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Logic Minimization for Arbitrary State Assignment 62 Current Result: 6 products, 14 literals. 11 11 Y2 X 11 X Z Y1* 11 11 Y1 X Y2* Previous Result: 5 products, 10 literals.

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Circuit for Arbitrary State Assignment 63 Y2 Y1 Y1 Y2 X Z Y2* Y1* CK CLEAR Comb. logic 42 transistors

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Best Encoding Strategy 64 minimum cost To determine the encoding with the minimum cost and delay, we need to: 1.Generate K-Maps for the next-state and output functions 2.Derive excitation equations from the next-state map. 3.Derive output equations from the output function map. 4.Implement above equations using two- level NAND gates. 5.Calculate cost and delay

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65 Optimizing Sequential Circuits by Retiming Netlist of Gates Netlist of gates and registers: Various Goals: – Reduce clock cycle time – Reduce area Reduce number of latches Inputs Outputs

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66 Retiming Problem –Pure combinational optimization can be myopic since relations across register boundaries are disregarded Solutions –Retiming: Move register(s) so that clock cycle decreases, or number of registers decreases andclock cycle decreases, or number of registers decreases and input-output behavior is preservedinput-output behavior is preserved –RnR: Combine retiming with combinational optimization techniques Move latches out of the way temporarilyMove latches out of the way temporarily optimize larger blocks of combinationaloptimize larger blocks of combinational

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Synchronous Logic Network … Synchronous Logic Network – Variables. – Boolean equations. – Synchronous delay annotation. Synchronous network graph – Vertices equations I/O, gates. – Edges dependencies nets. – Weights synch. delays registers.

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68 Circuit Representation Circuit representation: G(V,E,d,w) –V set of gates –E set of wires –d(v) = delay of gate/vertex v, (d(v) 0) –w(e) = number of registers on edge e, (w(e) 0)

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… Synchronous Logic Network

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70 Circuit Representation Example: Correlator (from Leiserson and Saxe) (simplified) Circuit (x, y) = 1 if x=y 0 otherwise Operation delay 3 + 7 Every cycle in Graph has at least one register i.e. no combinational loops. 0 33 0 0 0 0 2 Retiming Graph (Directed) 7 a b + Host

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71 Preliminaries For a path p : Clock cycle For correlator c = 13 Path with w(p)=0 0 33 0 0 0 0 2 7 Path Delay Path weight

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72 Movement of registers from input to output of a gate or vice versa A positive value corresponds to shifting registers from the outputs to inputs This should not affect gate functionality's Mathematical formulation: A retiming of a network G(V,E,W) is: an integer vertex labeling –r: V Z, an integer vertex labeling, that transforms G(V,E,W) into G’(V,E,W’), where for each edge e=(u,v), the weight after retiming w r (e) is given by: –w r (e) = w(e) + r(v) - r(u) for edge e = (u,v) Basic Operation Retime by +1 Retime by -1

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Sequential Logic Synthesis is an important phase of the Front End Tool for VLSI Circuits. Optimization of Sequential Circuits involves: State Minimization State Encoding Retiming State Minimization may be applied to completely specified Machines or Incompletely specified Machines. State Encoding utilizes different heuristics to further minimize the logic Retiming plays an important role in reducing the latency of the circuit. Summary 73

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