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RLH - Spring 1998ECE 611 Timing - 1 Basic Microprocessor Timing ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department of.

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Presentation on theme: "RLH - Spring 1998ECE 611 Timing - 1 Basic Microprocessor Timing ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department of."— Presentation transcript:

1 RLH - Spring 1998ECE 611 Timing - 1 Basic Microprocessor Timing ECE 611 Microprocessor Systems Dr. Roger L. Haggard, Associate Professor Department of Electrical and Computer Engineering Tennessee Technological University Spring 1998

2 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing Bus Timing - Read S0S2S4S1S3S5S6S7S0S1S2S3S4WWWWS5S6S7 Bus Cycle Mem/IO Read Bus Cycle (Slow) Mem/IO Read CLK Valid A(23 -1)Data In D(15 - 0) Addr Valid AS* Enable Data In LDS* UDS* Enable Data InRead R/W Read Ready WW DTACK* (Must Rise) States

3 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing Bus Timing - Write S0S2S4S1S3S5S6S7S0S1S2S3S4WWS5S6S7 Bus Cycle Mem/IO Write Bus Cycle (Slow) Mem/IO Write CLK Valid A(23 -1) Data Out D(15 - 0) Addr Valid AS* Latch Data LDS* UDS* Latch Data Write Enable R/W Write Enable Ready W DTACK*

4 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing Bus Timing - Read T1T2T3T4T1T2T3Tw T4 Bus Cycle Two Wait States States CLK Status A,BHE A(19-16) BHE (WR is kept high) Mem ReadI/O Input AData InA AD(15-0) Latch Address Latch Address ALE Mem I/O M / IO Read RD Receive DT/R Disable Enable Disable Enable DEN Ready Wait READY Valid AB(19-0) Data In DB(15-0)

5 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing Bus Timing - Write T1T2T3T4T1T2T3TwT4 Bus Cycle One Wait State CLK (RD is kept high) Mem WriteI/O Output Status A,BHE A(19-16) BHE AD(15-0) Data Out A A Latch Address Latch Address ALE MemI/O M / IO Write WR Latch Data Latch Data Transmit DT/R Disable Enable Disable Enable DEN Ready Wait READY Valid AB(19-0) Data Out DB(15-0)

6 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing Timing - Program Memory Read ALE PSEN Enable In P1P2 Machine Cycle XTAL2 S1S2S3S4S5S6 P1P2P1P2P1P2P1P2P1P2P1P2 S1 A[7-0] out Port 0 / AD[7-0] D[7-0] in A[7-0] out D[7-0] in A[15-8] Byte1 Port 2 / A[15-8] Byte2 (if needed)

7 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing Timing - Data Memory Read ALE PSEN Read Inst RD Read Data (data)(inst) A[7-0] out Port 0 / AD[7-0] D[7-0] in A[7-0] out D[7-0] in A[7-0] out (inst) (data) A[15-8] Port 2 / A[15-8] (data)(inst)

8 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing Timing - Data Memory Write ALE PSEN Read Inst WR Write Data A[7-0] out Port 0 / AD[7-0] D[7-0] in A[7-0] out A[7-0] out (data)(inst) (data) D[7-0] out A[15-8] Port 2 / A[15-8] (data)(inst)

9 RLH - Spring 1998ECE 611 Timing - 9 Memory Interfacing and Timing

10 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing - 10 Interface to 6116 static RAM (1) CPU A 01 -A 11 D 00 - D 15 A ( 10-0 ) D ( 7-0 ) Address busData bus Lower byte Upper byte D ( 7-0 ) A ( 10-0 ) D 00 - D 07 D 08 - D 15 RAM1 RAM (2K x8)

11 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing - 11 Interface to 6116 static RAM (2) CPU RAM1 RAM2 OE* R/W OE* CS* AS* R/W Low in a write cycle when AS* also low RAMCS* low when RAM1 or RAM2 addressed CS2 * LDS* UDS* A 12 - A 23 Address decoder CS1 * Low during access to RAM2 when UDS* low Low during access to RAM1 when LDS* low DTACK * DTACK Gen Low when either RAM1 or RAM2 selected delays DTACK* to introduce wait states 6116 (2K x8)

12 RLH - Fall 1997RLH - Spring 1998ECE 611 Timing - 12 Interface 8086 to 6116 static RAM 8086 A ____ BHE ALE A ( 10-0 ) D ( 7-0 ) __ R/W OE* CS* A ( 10-0 ) __ R/W OE* CS* D D ( 7-0 ) 20 Latch Addr Decoder A ( ) 21 A 0, BHE * A ( ) A ( 11-1 ) __ M/IO ___ RD ___ WR READY low byte (even) hi byte (odd) D ( 7-0 ) D ( ) 16 A0A0 RAMCS* MEM * BHE* Wait State Gen 6116 (2K x8)


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