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Lecture 8 Sequential Logic Prof. Sin-Min Lee Department of Computer Science.

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Presentation on theme: "Lecture 8 Sequential Logic Prof. Sin-Min Lee Department of Computer Science."— Presentation transcript:

1 Lecture 8 Sequential Logic Prof. Sin-Min Lee Department of Computer Science

2 Implement D Flip-flop by T Flip-flop DT Q Q T = D Q’ + D’ Q D D’ T

3 Implement JK Flip-flop by D Flip-flop J K Q D = J Q’ + K’ Q D 0 1 J K Q DQ+Q J K Q Q’

4 Implement JK Flip-flop by T Flip-flop J K Q T = J Q’ + K Q T 0 1 J K TQ+Q Q Q’ J K Q Q Q+Q+ J KQ+Q Q 0 1 Q’

5 Implement T Flip-flop by JK Flip-flop 0 X 1 X X 1 X 0 J K T Q Q Q+ 0 1 T Q X 1 X 0 1 T Q 0101 X 0 X J = T K = T

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28 Random-Access Memory Can read and write at any point in memory Implemented using D Flip-Flops Each row contains 16 Flip-Flops A Decoder

29 Binary Counter Holds each pulse in memory Each pulse add another number Binary format

30 Register Used to hold one item of information CPU’s have many registers AX is an example in Assembly

31 Clocks and Sequencers To perform operations a CPU often requires a specific sequence of sub operations A sequencer is used to make sure operations happen in correct order A clock is a circuit that outputs 0’s and 1’s at specific frequencies

32 Real World Application The RAM discussed is a model for a chip that can actually be found in a computer The binary counter can be bought at tronics.com/webtronics/74hc161n.html for 45 cents each tronics.com/webtronics/74hc161n.html The Flip-Flop circuits are models of usable chips

33 State Diagrams A state diagram: –Each state is represented by a circled vertex –Each row of the state table is shown as directed arc J’ Y

34 Important Rule for State Diagram State diagram has same situation as state table. Their conditions should be mutually exclusive, no input values should meet the condition of more than one arc.

35 The Alarm Clock Present state AlarmWeekdayNext state Turn off alarm OnXAwake in bed YesAsleep Awake in bedOffYes Awake and up No Awake in bed Off No AsleepNo

36 State Diagram for The Alarm Clock (a) Awake in bedAsleep Alarm’ Alarm Awake and up 1 (Always) Alarm Alarm’ /\ Weekday’ Alarm’ /\ Weekday Turn off Alarm = Yes ( a )

37 The alarm clock problem with inaction states Present stateAlarmWeekdayNext stateTurn off alarm AsleepOffX Asleep No Asleep On Awake in bed Yes Awake in bed On X Awake in bed yes Awake in bed OffYesAwake and upNo Awake in bedOffNoAsleep No Awake and upX X No X

38 State Diagram for The Alarm Clock State Diagram for The Alarm Clock (b) ( b ) AsleepAwake in bed Awake and up Alarm’ / 0 Alarm / 1 Alarm’ /\ Weekday’ / 0 1 (Always) / 0 Alarm’ /\ Weekday / 0 Alarm / 1 1 = yes turn off alarm (output) 0 – no turn off alarm (output)

39 State Tables for The JK Flip-Flop ( a ) Present State Y Z Z Z Z Y Y Y JK Next StateQ Y Y Z Z Z Y Z Y

40 Condition in Terms of J and K Z J K J’K’ Q=0 Q=1 Y

41 Mealy and Moore Machines A finite state machine can represent outputs in one of two ways –Moore Machines –Mealy Machines

42 Moore Machines –Moore Machines Associates its outputs with the states. Output values depend only on the state and not on the transitions. It requires less hardware to produce the output values It is well suited for representing the control units of microprocessors and cpu.

43 State Diagram for The Alarm Clock (a) Awake in bedAsleep Alarm’ Alarm Awake and up 1 (Always) Alarm Alarm’ /\ Weekday’ Alarm’ /\ Weekday Turn off Alarm = Yes Moore Machine

44 Mealy Machines –Mealy Machines Associates outputs with the transitions. It depends on both its state and its input values

45 State Diagram for The Alarm Clock State Diagram for The Alarm Clock (b) Mealy Machine AsleepAwake in bed Awake and up Alarm’ / 0 Alarm / 1 Alarm’ /\ Weekday’ / 0 1 (Always) / 0 Alarm’ /\ Weekday / 0 Alarm / 1

46 Designing State Diagrams Counter String Checker Toll Booth

47 Modulo 6 Counter A modulo 6 counter is a 3-bit counter that counts through the sequence. – … – … Unlike a regular 3-bit counter 110(6) and 111(7) do not count

48 State Table for The Modulo 6 Counter Present StateNext StateCV 2 V 1 V 0 U S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 S4S4 S4S4 S5S5 S5S S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 S4S4 S4S4 S5S5 S5S5 S0S

49 State Diagram for The Modulo 6 Counter (Mealy) S0S0 S5S5 S1S1 S4S4 S2S2 S3S3 0 / / / / / / / / / / / / 1000 ( a ) Mealy

50 State Diagram for The Modulo 6 Counter (Moore) S5S5 S0S0 S1S1 S4S4 S2S2 S3S3 U’ C=1 V =000 U C=0 V=0010 U C=0 V=010 U C=0 V=011 U C=0 V=100 U C=0 V=101 ( b ) Moore

51 String Checker A String Checker inputs a string of bits, one bits per clock cycle. It checks bits 1,2, and 2, then 2,3,and 4 and so forever

52 State Table For String Checker Present State S 0 S1 S 2 S 3 S 4 S 5 S 6 S LNext State S0S1S2S3S4S5S6S7S0S1S2S3S4S5S6S7S0S1S2S3S4S5S6S7S0S1S2S3S4S5S6S7 M

53 State Diagrams for the String Checker ( Mealy) S3S3 S7S7 S0S0 S1S1 S4S4 S6S6 S5S5 S2S2 0/0 1/0 0/0 1/0 0/1 1/0 Mealy

54 State Diagrams for the String Checker (Moore) S7S7 S0S0 S6S6 S5S5 S4S4 S3S3 S2S2 S1S1 M=1 I’ M=0 I’ M=0 I I I I I’ I I I I M=0 Moore


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