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**Multicycle Processor Design for Dummies**

By Jonathan Richard

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**Overview Instruction Set Architecture (ISA) Multicycle Datapath**

Control

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**ISA Instruction Format 16 total instructions 8 total registers**

I-code capable of ranges from -32 to 31 as opposed to -8 to 7 for 4 bits R opcode rs rt rd blank 4 bits 3 bits I addr 6 bits J 12 bits

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**ISA LIST Instruction Type Opcode Example Meaning sll I sll $s2, $s4, 1**

sll $s2, $s4, 1 $s2 = $s4 << 1 AND R 1 and $s2, $s4, $s3 $s2 = $s4 & $s3 OR 2 or $s2, $s4, $s3 $s2 = $s4 | $s3 add 3 add $s2, $s4, $s3 $s2 = $s4 + $s3 subtract 4 sub $s2, $s4, $s3 $s2 = $s4 - $s3 add immediate 5 addi $s2, $s4, 20 $s2 = $s4 + 20 load word 6 lw $s2,20($s4) $s2 = Memory[ $s4 + 20] store word 7 sw $s2,20($s4) Memory[$s4 + 20] = $s2 branch on not equal 8 bne $s2, $s4, 25 if($s2 != $s4) go to PC+4+100 branch on equal 9 beq $s2, $s4, 25 if($s2 ==$s4) go to PC+4+100 set on less than 10 slt $s2, $s4, $s3 if($s4 < $s3) $s2 = 1; else $s2 = 0 set on less than immed 11 slti $s2, $s4, 20 if($s4<20) $s2 = 1; else $s2 = 0 Jump J 12 j 2500 go to 10000 jump register 13 jr $ra go to $ra jump and link 14 jal 2500 $ra = PC + 4; go to 10000 HALT H 15 HT stops processor

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**Multicycle Datapath PC Instr Mem MUX I R M D RE G F L E A B ALU**

Sign Ext Ctrl U PC Write 1 111 Mem Read Write lorD IR Write Mem2Reg Reg Write ALU Src A ALU Src B PC Source OP Reg Dest Control

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**Control Rom 2 Rom 1 Control PLA Mux Add 19 “0001” 2 1x4 Flip Flop**

“0000” “0001” 4 19 2

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**Decode, Reg Fetch, Branch Addr**

Control FSM 1 2 3 4 5 6 7 9 12 10 11 13 14 Lw/sw Lw Sw R I J Jal Jr Fetch, PC Decode, Reg Fetch, Branch Addr ALU Op Write Reg Write Co Addr, ALU Op, Read Mem Comp Addr Reg 8 B

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Control PLA when "0000" => data_out<= " ";--state 0 Then 1 to go to state 1 when "0001" => data_out<= " ";--state 1 Then lw/sw/R/B/J when "0010" => data_out<= " ";--state 2 lw/sw cycle 3 Then lw or sw when "0011" => data_out<= " ";--state 3 lw cycle 4 Then state 4 when "0100" => data_out<= " ";--state 4 lw cycle 5 Then state 0 when "0101" => data_out<= " ";--state 5 sw cycle 4 Then state 0 when "0110" => data_out<= " ";--state 6 R cycle 3 Then state 7 when "0111" => data_out<= " ";--state 7 R cycle 4 Then state 0 when "1000" => data_out<= " ";--state 8 Be cycle 3 Then state 0 when "1001" => data_out<= " ";--state 9 J cycle 3 Then state 0 when "1010" => data_out<= " ";--state 10 I cycle 3 Then state 11 when "1011" => data_out<= " ";--state 11 I cycle 4 Then state 0 when "1100" => data_out<= " ";--state 12 Jr cycle 3 Then state 0 when "1101" => data_out<= " ";--state 13 Jal cycle 3 Then state 14 when "1110" => data_out<= " ";--state 14 Jal cycle 4 Then state when others => data_out<= " "; -- start at state 0

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**Control Output Pins Control Name 16,15 RegDst 8 IRWrite 14 RegWrite 7**

PCWrite 13 ALU Src A 6 PCWriteCond 12 MemRead 5,4 ALU Op 11 MemWrite 3,2 ALU Src B 10 MemtoReg 1,0 PC Source 9 lorD

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ALU Control if ( ALUOp = "01" ) then --cycle case IRCode is when "0000" => data_out<= "100";--sll when "0001" => data_out<= "010";--And when "0010" => data_out<= "011";--xor when "0011" => data_out<= "000";--add when "0100" => data_out<= "001";--sub when "0101" => data_out<= "000"; when "0110" => data_out<= "000"; when "0111" => data_out<= "000"; when "1000" => data_out<= "111";--bne when "1001" => data_out<= "110";--beq when "1010" => data_out<= "101";--stl when "1011" => data_out<= "101";--stli when "1100" => data_out<= "000"; when "1101" => data_out<= "000"; when "1110" => data_out<= "000"; when "1111" => data_out<= "000"; when others => data_out<= "000"; end case; else data_out<= "000"; end if;

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