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Multicycle Processor Design for Dummies By Jonathan Richard

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Overview Instruction Set Architecture (ISA) Multicycle Datapath Control

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ISA Instruction Format 16 total instructions 8 total registers I-code capable of ranges from -32 to 31 as opposed to -8 to 7 for 4 bits Ropcodersrtrdblank 4 bits3 bits Iopcodersrtaddr 4 bits3 bits 6 bits Jopcodeaddr 4 bits12 bits

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ISA LIST InstructionTypeOpcodeExampleMeaning sllI0sll $s2, $s4, 1$s2 = $s4 << 1 ANDR1and $s2, $s4, $s3$s2 = $s4 & $s3 ORR2or $s2, $s4, $s3$s2 = $s4 | $s3 addR3add $s2, $s4, $s3$s2 = $s4 + $s3 subtractR4sub $s2, $s4, $s3$s2 = $s4 - $s3 add immediateI5addi $s2, $s4, 20$s2 = $s load wordI6lw $s2,20($s4)$s2 = Memory[ $s4 + 20] store wordI7sw $s2,20($s4)Memory[$s4 + 20] = $s2 branch on not equalI8bne $s2, $s4, 25if($s2 != $s4) go to PC branch on equalI9beq $s2, $s4, 25if($s2 ==$s4) go to PC set on less thanR10slt $s2, $s4, $s3if($s4 < $s3) $s2 = 1; else $s2 = 0 set on less than immedI11slti $s2, $s4, 20if($s4<20) $s2 = 1; else $s2 = 0 JumpJ12j 2500go to jump registerJ13jr $rago to $ra jump and linkJ14jal 2500$ra = PC + 4; go to HALTH15HTstops processor

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Multicycle Datapath

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Control Rom 2Rom 1 Control PLA Mux 1x4 Flip Flop Add “0000” “0001”

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Control FSM Lw/sw Lw Sw RI J Jal Jr Fetch, PC Decode, Reg Fetch, Branch Addr ALU Op Write Reg Write PC Co Addr, PC ALU Op, PC Read Mem Comp Addr Write Reg Write Mem 8 Comp Addr B

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Control PLA when "0000" => data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out<= " "; -- start at state 0

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Control Output PinsControl NamePinsControl Name 16,15RegDst8IRWrite 14RegWrite7PCWrite 13ALU Src A6PCWriteCond 12MemRead5,4ALU Op 11MemWrite3,2ALU Src B 10MemtoReg1,0PC Source 9lorD

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ALU Control if ( ALUOp = "01" ) then --cycle 3 case IRCode is when "0000" => data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out data_out<= "000"; end case; else data_out<= "000"; end if;

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Questions?

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