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1 FSM Word Problems Notes: Review for Test #2 – Monday Studio #8: Reading assignment is required & due next week Today: First Hour: Finite string recognizer, Complex counter –Section 8.5 of Katz’s Textbook –In-class Activity #1 Second Hour: Traffic signal controller, Digital combination lock Section 8.5 of Katz’s Textbook –In-class Activity #2

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2 Katz Material not Covered CoCO doesn't cover everything in Katz. Omitted material includes: ASM charts The ABEL language all of Chapter 9 is skipped

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3 Word Problems One of the most difficult problems is making an imprecise description of a finite state machine into a precise one. Have you covered all the states? Omissions can cause failures, crashes, death and destruction, etc. This is the Hardware equivalent of a Software programming error.

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4 Finite String Recognizer One input: X One output: Z Description: –Z is 1 if the 3 previous input bits are 010, and 100 has never been seen. Unstated assumptions: –RESET starts the FSM at the "reset" state –Z is asserted when the following bit is seen. A Moore Machine implementation. Serial Finite State Machine

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5 Example X: Z: Z is 0 even though the three previous inputs are 010, because 100 was seen earlier.Z is 0 even though the three previous inputs are 010, because 100 was seen earlier. Serial Behavior

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6 S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] Reset ,1 Formal Design Create sequences of states for the strings that the machine recognizes: 010 and and 100. S0Note we reset to S0. Consider the unlabelled transitions. State Transition Diagram

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7 S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] Reset 01? State S3 S3Where do we go from S3? 101 S2A 1 means the last 3 bits are 101, so go to S S6A 0 means we’ve seen 100, so go to S ,1 Diagram Development

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8 S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] Reset , ? States S1 and S4 S1 1Loop in S1 until we see our first 1. S4 0Loop in S4 until we see our first 0. 01? ? Diagram Development

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9 States S2 and S5 S S2 means the last 2 bits are 01, which may be a prefix of S4If the next bit is 1, the last 2 bits are now 11, maybe a prefix of 100. That’s S4. S S2S5: Last 2 bits are 10. If next bit is 1, maybe that’s a prefix for 010. Go to S2. S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] Reset , ? ? 0? 01? Diagram Development

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10 Review of Design Steps Write sample inputs and outputs to understand it. Write sequences of states and transitions for the strings that the FSM is to recognize. Add missing transitions, using existing states when possible. Verify that the state diagram matches the FSM. Katz's Method

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11 Complex Counter MDesign a 3-bit counter, with one input bit, a mode, M. M = 0If M = 0, step to the next binary number in the sequence 000, 001, 010, 011, 100, 101, 110, 111, … M = 1If M = 1, step to the next Gray code number in the sequence 000, 001, 011, 010, 110, 111, 101, 100,...

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12 Try Some Sample Inputs Note that we can switch modes at any time. Mode Input M Current State Next State (Z2 Z1 Z0)

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13 Reset S0 [000] S1 [001] S2 [010] S3 [011] S4 [100] S5 [101] S6 [110] S7 [111] Formal Representation One state for each output combination Add appropriate arcs for the mode control

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14 Do Activity #1 Now S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] Reset , ? ? 0? 01? Reset S0 [000] S1 [001] S2 [010] S3 [011] S4 [100] S5 [101] S6 [110] S7 [111] FSM String Recognizer, Z=1 if 010 is seen, but 100 not seen before Complex Counter

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15 Diagram of Intersection Highway Farmroad HL FL C C

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16 Traffic Light Controller A busy highway is intersected by a little-used farm road. CDetectors C sense the presence of cars waiting on the farm road. GreenWith no car is on farm road, the lights remain Green in the highway direction. GreenYellowRed GreenIf vehicle is on the farm road, highway lights go from Green to Yellow to Red, allowing the farm road lights to become Green. GreenThese stay Green only as long as a farm road car is detected but never longer than a set time interval. Green YellowRedGreenWhen these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to Green. GreenEven if farm road vehicles are waiting, the highway gets at least a set interval as Green.

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17 Available Timers TSTL STAssume you have an interval timer that generates a short time pulse (TS) and a long time pulse (TL) in response to a start timer (ST) signal. TSYellowTL GreenTS is to be used for timing Yellow lights and TL for Green lights

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18 Tabulate Inputs & Outputs Input SignalresetCTSTL Output Signal HG, HY, HR FG, FY, FR ST Description place FSM in initial state detect vehicle on farm road short time interval expired long time interval expired Description assert green/yellow/red highway lights assert green/yellow/red farm road lights start timing a short or long interval

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19 Tabulate Unique States Some light configurations imply others. State S0 S1 S2 S3 Description Highway green (farmroad red) yellow Highway yellow (farmroad red) Farmroad green (highway red) yellow Farmroad yellow (highway red)

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20 List Assumptions Reset places timer in S0, highway green and farm road red. Reset also starts the timer. Stay in S0 as long as no one is on the farm road. Even if there is a farm road vehicle, the highway stays green at least long as the long time interval. (Unstated in Katz) There will never be a bicycle or pedestrian on the farm road.

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21 Traffic Signal State Diagram Reset TL + C S0 TLC/ST S1S3 S2 S0: HG HY S1: HY S2: FG FY S3: FY TL: long time interval expired C: detect vehicle on farmroad

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22 Traffic Signal State Diagram Reset TL + C S0 TLC/ST TS S1S3 S2 TS/ST S0: HG HY S1: HY S2: FG FY S3: FY TS: short time interval expired ST: start timing a short or long interval

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23 Traffic Signal State Diagram Reset TL + C S0 TLC/ST TS S1S3 S2 TS/ST TL + C/ST TL C S0: HG HY S1: HY S2: FG FY S3: FY TL: long time interval expired C: detect vehicle on farm road ST: start timing a short or long interval

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24 Traffic Signal State Diagram Reset TL + C S0 TLC/ST TS S1S3 S2 TS/ST TL + C/ST TS TL C S0: HG HY S1: HY S2: FG FY S3: FY TS: short time interval expired ST: start timing a short or long interval

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25 Combination Lock 3 bit serial lock controls entry to locked room. Inputs are RESET, ENTER, 2 position switch for bit of KEY data. Locks generates an UNLOCK signal when KEY matches internal combination. ERROR light illuminated if KEY does not match combination. Sequence is: –(1) Press ENTER, –(2) enter KEY bit, –(3) Press ENTER, –(4) repeat (2) & (3) two more times. In the last round, it is not necessary to press ENTER.

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26 Incomplete Specification Problem specification is incomplete: – how do you set the internal combination? – exactly when is the ERROR light asserted?

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27 Why is it just possibly a bad idea to indicate an error immediately on seeing the first bad bit ? Make Assumptions Make reasonable assumptions, decide whether –combination is hardwired into logic or stored in a register? –error is asserted as soon as an error is detected or waits until the full combination has been entered? Our design: combination is stored in a register and error is asserted after the full combination has been entered

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28 Block Diagram of Lock Inputs: Reset, Enter, Key-In, L0, L1, L2 Outputs: Unlock, Error Operator Data Internal Combination Internal Combination

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29 Enumerate the States What sequences lead to opening the door? Do error conditions on a second pass …

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30 State Diagram of Lock Enter Comp1 Error1 KI L 1 KI = L 1 Enter Idle1Idle1' Comp2Error2 KI L 2 KI = L 2 Done [Unlock] Error3 [Error] Reset Start Reset Reset + Enter Reset Enter Start Comp0 KI = L 0 KI L 0 Enter Idle0Idle0'

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31 Do Activity #2 Now Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: – Sec , skim 11.2 of Katz, omit the ABEL and ASM descriptions This reading is necessary for getting points in the Studio Activity!

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