Presentation on theme: "FSM Word Problems Today:"— Presentation transcript:
1 FSM Word Problems Today: Notes: Review for Test #2 – MondayStudio #8: Reading assignment is required & due next weekToday:First Hour: Finite string recognizer, Complex counterSection 8.5 of Katz’s TextbookIn-class Activity #1Second Hour: Traffic signal controller, Digital combination lockIn-class Activity #2
2 Katz Material not Covered CoCO doesn't cover everything in Katz.Omitted material includes:ASM chartsThe ABEL languageall of Chapter 9 is skipped
3 Word ProblemsOne of the most difficult problems is making an imprecise description of a finite state machine into a precise one.Have you covered all the states?Omissions can cause failures, crashes, death and destruction, etc.This is the Hardware equivalent of a Software programming error.
4 Finite String Recognizer Serial Finite State MachineOne input: XOne output: ZDescription:Z is 1 if the 3 previous input bits are 010, and 100 has never been seen.Unstated assumptions:RESET starts the FSM at the "reset" stateZ is asserted when the following bit is seen. A Moore Machine implementation.
5 Example Serial Behavior X: 0 0 1 0 1 0 1 0 0 1 0 Z:Z is 0 even though the three previous inputs are 010, because 100 was seen earlier.
6 State Transition Diagram Formal DesignState Transition DiagramResetS0Create sequences of states for the strings that the machine recognizes:010 and 100.Note we reset to S0.Consider the unlabelled transitions.1S1S41S2S50,1S3S6
7 State S3 Diagram Development 1 1 01? 1 0,1 010 100 Reset S0  S1 S4 1Where do we go from S3?A 1 means the last 3 bits are 101, so go to S2.A 0 means we’ve seen 100, so go to S6.S1S41S2S501?10,1S3S6010100
8 States S1 and S4 Diagram Development 1 1? 1 0? 1 01? 1 0,1 010 100 ResetS0Loop in S1 until we see our first 1.Loop in S4 until we see our first 0.1S11?S410?1S2S501?10,1S3S6010100
9 States S2 and S5 Diagram Development 1? 1 0? 01? 10? 0,1 010 100 S0 S1S2S3S4S5S6Reset10,110?1?0?01?100010S2 means the last 2 bits are 01, which may be a prefix of 010.If the next bit is 1, the last 2 bits are now 11, maybe a prefix of That’s S4.S5: Last 2 bits are 10. If next bit is 1, maybe that’s a prefix for Go to S2.
10 Review of Design Steps Katz's Method Write sample inputs and outputs to understand it.Write sequences of states and transitions for the strings that the FSM is to recognize.Add missing transitions, using existing states when possible.Verify that the state diagram matches the FSM.
11 Complex Counter Design a 3-bit counter, with one input bit, a mode, M. If M = 0, step to the next binary number in the sequence 000, 001, 010, 011, 100, 101, 110, 111, …If M = 1, step to the next Gray code number in the sequence 000, 001, 011, 010, 110, 111, 101, 100, ...
12 Try Some Sample Inputs Note that we can switch modes at any time. Mode InputM1CurrentStateNext State(Z2 Z1 Z0)
13 Formal Representation ResetS0S1S2S3S4S5S6S71One state for each output combinationAdd appropriate arcs for the mode control
14 Do Activity #1 NowResetS0S1S2S3S4S5S6S71ResetS01S11?S4110?11S2S501?10?1S3S60,1010100FSM String Recognizer, Z=1 if010 is seen, but 100 not seen beforeComplex Counter
16 Traffic Light Controller A busy highway is intersected by a little-used farm road.Detectors C sense the presence of cars waiting on the farm road.With no car is on farm road, the lights remain Green in the highway direction.If vehicle is on the farm road, highway lights go from Green to Yellow to Red, allowing the farm road lights to become Green.These stay Green only as long as a farm road car is detected but never longer than a set time interval.When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to Green.Even if farm road vehicles are waiting, the highway gets at least a set interval as Green.
17 Available TimersAssume you have an interval timer that generates a short time pulse (TS) and a long time pulse (TL) in response to a start timer (ST) signal.TS is to be used for timing Yellow lights and TL for Green lights
18 Tabulate Inputs & Outputs Input SignalresetCTSTLOutput SignalHG, HY, HRFG, FY, FRSTDescriptionplace FSM in initial statedetect vehicle on farm roadshort time interval expiredlong time interval expiredassert green/yellow/red highway lightsassert green/yellow/red farm road lightsstart timing a short or long interval
19 Tabulate Unique States Some light configurations imply others.StateS0S1S2S3DescriptionHighway green (farmroad red)Highway yellow (farmroad red)Farmroad green (highway red)Farmroad yellow (highway red)
20 List AssumptionsReset places timer in S0, highway green and farm road red.Reset also starts the timer.Stay in S0 as long as no one is on the farm road.Even if there is a farm road vehicle, the highway stays green at least long as the long time interval.(Unstated in Katz) There will never be a bicycle or pedestrian on the farm road.
21 Traffic Signal State Diagram TL + CResetS0S0: HGS1: HYS2: FGS3: FYTL•C/STS1S3TL: long time interval expiredS2C: detect vehicle on farmroad
22 Traffic Signal State Diagram TL + CResetS0S0: HGS1: HYS2: FGS3: FYTL•C/STTSS1S3TS/STTS: short time interval expiredS2ST: start timing a short or longinterval
23 Traffic Signal State Diagram TL + CResetS0S0: HGS1: HYS2: FGS3: FYTL•C/STTSS1S3TS/STTL + C/STS2TL: long time interval expiredC: detect vehicle on farm roadTL • CST: start timing a short or longinterval
24 Traffic Signal State Diagram TL + CResetS0S0: HGS1: HYS2: FGS3: FYTL•C/STTS/STTSS1S3TSTS/STTL + C/STS2TS: short time interval expiredST: start timing a short or longintervalTL • C
25 Combination Lock 3 bit serial lock controls entry to locked room. Inputs are RESET, ENTER, 2 position switch for bit of KEY data.Locks generates an UNLOCK signal when KEY matches internal combination.ERROR light illuminated if KEY does not match combination.Sequence is:(1) Press ENTER,(2) enter KEY bit,(3) Press ENTER,(4) repeat (2) & (3) two more times. In the last round, it is not necessary to press ENTER.
26 Incomplete Specification Problem specification is incomplete:how do you set the internal combination?exactly when is the ERROR light asserted?
27 Make Assumptions Make reasonable assumptions, decide whether combination is hardwired into logic or stored in a register?error is asserted as soon as an error is detected or waits until the full combination has been entered?Our design: combination is stored in a register and error is asserted after the full combination has been enteredWhy is it just possibly a bad idea to indicate an error immediately on seeing the first bad bit ?
28 Block Diagram of Lock Operator Data Internal Combination Inputs: Reset,Enter,Key-In,L0, L1, L2Outputs:Unlock,Error
29 Enumerate the States What sequences lead to opening the door? Do error conditions on a second pass …
30 State Diagram of Lock Enter Enter Comp1 Error1 KI L1 KI = L1 Enter Idle1Idle1'Reset + EnterResetEnterEnterStartComp2Error2Reset • EnterKI L2KI = L2Comp0ResetResetError3KI = L0KI L0Done[Error][Unlock]EnterEnterResetIdle0Idle0'ResetStartStart
31 Do Activity #2 Now For Next Class: Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!!For Next Class:Bring Randy Katz Textbook, & TTL Data BookRequired Reading:Sec , skim 11.2 of Katz, omit the ABEL and ASM descriptionsThis reading is necessary for getting points in the Studio Activity!