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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 1 Sequential Logic Optimization zState Minimization yAlgorithms for State Minimization zState, Input, and Output Encodings yMinimize the Next State and Output logic

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 2 Optimization in Context zUnderstand the word specification zDraw a picture zDerive a state diagram and Symbolic State Table zDetermine an implementation approach (e.g., gate logic, ROM, FPGA, etc.) zPerform STATE MINIMIZATION zPerform STATE ASSIGNMENT zMap Symbolic State Table to Encoded State Tables for implementation (INPUT and OUTPUT encodings) You can specify a specific state assignment in your Verilog code through parameter settings

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 3 Finite State Machine Optimization zState Minimization yFewer states require fewer state bits yFewer bits require fewer logic equations zEncodings: State, Inputs, Outputs yState encoding with fewer bits has fewer equations to implement xHowever, each may be more complex yState encoding with more bits (e.g., one-hot) has simpler equations xComplexity directly related to complexity of state diagram yInput/output encoding may or may not be under designer control

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 4 Algorithmic Approach to State Minimization zGoal – identify and combine states that have equivalent behavior zEquivalent States: ySame output yFor all input combinations, states transition to same or equivalent states zAlgorithm Sketch y1. Place all states in one set y2. Initially partition set based on output behavior y3. Successively partition resulting subsets based on next state transitions y4. Repeat (3) until no further partitioning is required xstates left in the same set are equivalent yPolynomial time procedure

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 5 Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1S200 0S1S3S400 1S2S5S600 00S3S0S000 01S4S0S010 10S5S0S000 11S6S0S010 State Minimization Example zSequence Detector for 010 or 110 S0 S3 S2S1 S5S6S4 1/00/0 1/0 0/1 0/01/00/0 1/0 0/0 1/0 0/1 1/0 0/0

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 6 ( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 ) ( S0 S1 S2 ) ( S3 S5 ) ( S4 S6 ) ( S0 ) ( S1 S2 ) ( S3 S5 ) ( S4 S6 ) Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1S200 0S1S3S400 1S2S5S600 00S3S0S000 01S4S0S010 10S5S0S000 11S6S0S010 S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6 Method of Successive Partitions

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 7 Input Next State Output SequencePresent StateX=0X=1X=0X=1 ResetS0S1'S1'00 0 + 1S1'S3'S4'00 X0S3'S0S000 X1S4'S0S010 Minimized FSM zState minimized sequence detector for 010 or 110 S0 S1’ S3’ S4’ X/0 1/0 0/1 0/0 X/0 7 States reduced to 4 States 3 bit encoding replaced by 2 bit encoding

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 8 Another Example z4-Bit Sequence Detector: output 1 after each 4-bit input sequence consisting of the binary strings 0110 or 1010

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 9 State Transition Table zGroup states with same next state and same outputs S’ 10

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 10 Iterate the Row Matching Algorithm S’ 7

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 11 Iterate One Last Time S’ 3 S’ 4

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 12 Final Reduced State Machine 15 states (min 4 FFs) reduced to 7 states (min 3 FFs)

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 13 symbolic state transition table present next state output state00011011 S0S0S1S2S31 S1S0S3S1S40 S2S1S3S2S41 S3S1S0S4S50 S4S0S1S2S51 S5S1S4S0S50 inputs here More Complex State Minimization zMultiple input example 10 01 11 00 01 11 10 01 11 00 10 00 11 00 11 10 01 10 11 01 00 S0 [1] S2 [1] S4 [1] S1 [0] S3 [0] S5 [0] 01

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 14 S0-S1 S1-S3 S2-S2 S3-S4 S0-S0 S1-S1 S2-S2 S3-S5 S0-S1 S3-S0 S1-S4 S4-S5 S0-S1 S3-S4 S1-S0 S4-S5 S1-S0 S3-S1 S2-S2 S4-S5 S4-S0 S5-S5 S1-S1 S0-S4 minimized state table (S0==S4) (S3==S5) present next state output state00011011 S0'S0'S1S2S3'1 S1S0'S3'S1S3'0 S2S1S3'S2S0'1 S3'S1S0'S0'S3'0 Minimized FSM zImplication Chart Method yCross out incompatible states based on outputs yThen cross out more cells if indexed chart entries are already crossed out S1 S2 S3 S4 S5 S0S1S2S3S4 present next state output state00011011 S0S0S1S2S31 S1S0S3S1S40 S2S1S3S2S41 S3S1S0S4S50 S4S0S1S2S51 S5S1S4S0S50

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 15 Minimizing Incompletely Specified FSMs zEquivalence of states is transitive when machine is fully specified zBut its not transitive when don't cares are present e.g.,stateoutput S0– 0S1 is compatible with both S0 and S2 S11 –but S0 and S2 are incompatible S2– 1 zNo polynomial time algorithm exists for determining best grouping of states into equivalent sets that will yield the smallest number of final states

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 16 XQ1Q0Q1+Q0+000000010001100100011011111111–1000XQ1Q0Q1+Q0+000000010001100100011011111111–1000 Q 1 + = X (Q 1 xor Q 0 ) Q 0 + = X Q 1 ’ Q 0 ’ Minimizing States May Not Yield Best Circuit zExample: edge detector - outputs 1 when last two input changes from 0 to 1 00 [0] 11 [0] 01 [1] X’ X X X

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 17 Another Implementation of Edge Detector z"Ad hoc" solution - not minimal but cheap and fast 00 [0] 10 [0] 01 [1] X’X X X X 11 [0] X’

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 18 State Assignment zChoose bit vectors to assign to each “symbolic” state yWith n state bits for m states there are 2 n ! / (2 n – m)! [log n <= m <= 2 n ] y2 n codes possible for 1st state, 2 n –1 for 2nd, 2 n –2 for 3rd, … yHuge number even for small values of n and m xIntractable for state machines of any size xHeuristics are necessary for practical solutions yOptimize some metric for the combinational logic xSize (amount of logic and number of FFs) xSpeed (depth of logic and fanout) xDependencies (decomposition)

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 19 State Assignment Strategies zPossible Strategies ySequential – just number states as they appear in the state table yRandom – pick random codes yOne-hot – use as many state bits as there are states (bit=1 –> state) yOutput – use outputs to help encode states yHeuristic – rules of thumb that seem to work in most cases zNo guarantee of optimality – another intractable problem

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 20 One-hot State Assignment zSimple yEasy to encode, debug zSmall Logic Functions yEach state function requires only predecessor state bits as input zGood for Programmable Devices yLots of flip-flops readily available ySimple functions with small support (signals its dependent upon) zImpractical for Large Machines yToo many states require too many flip-flops yDecompose FSMs into smaller pieces that can be one-hot encoded zMany Slight Variations to One-hot yOne-hot + all-0

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 21 State Maps and Counting Bit Changes Bit Change Heuristic S0S0 S1S1 S2S2 S3S3 S4S4 01 S0 -> S1: 2 1 S0 -> S2: 3 1 S1 -> S3: 3 1 S2 -> S3: 2 1 S3 -> S4: 1 1 S4 -> S1: 2 2 Total: 13 7

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 22 IQQ+OiacjibckIQQ+Oiacjibck IQQ+OiabjkaclIQQ+Oiabjkacl IQQ+OiabjicdjIQQ+Oiabjicdj c = i * a + i * b b = i * a c = k * a j = i * a + i * c b = i * a d = i * c i / j i / k a b c a bc i / j k / l bd i / j a c Adjacency Heuristics for State Assignment zAdjacent codes to states that share a common next state yGroup 1's in next state map zAdjacent codes to states that share a common ancestor state yGroup 1's in next state map zAdjacent codes to states that have a common output behavior yGroup 1's in output map

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 23 Heuristics for State Assignment Successor/Predecessor Heuristics z High Priority: S’ 3 and S’ 4 share common successor state (S 0 ) z Medium Priority: S’ 3 and S’ 4 share common predecessor state (S’ 1 ) z Low Priority: y0/0: S 0, S’ 1, S’ 3 y1/0: S 0, S’ 1, S’ 3, S’ 4

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 24 Heuristics for State Assignment

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 25 Another Example High Priority: S’ 3, S’ 4 S’ 7, S’ 10 Medium Priority: S 1, S 2 2 x S’ 3, S’ 4 S’ 7, S’ 10 Low Priority: 0/0: S 0, S 1, S 2, S’ 3, S’ 4, S’ 7 1/0: S 0, S 1, S 2, S’ 3, S’ 4, S’ 7, S 10

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 26 Example Continued z Choose assignment for S0 = 000 z Place the high priority adjacency state pairs into the State Map z Repeat for the medium adjacency pairs z Repeat for any left over states, using the low priority scheme Two alternative assignments at the left

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 27 Why Do These Heuristics Work? zAttempt to maximize adjacent groupings of 1’s in the next state and output functions

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 28 General Approach to Heuristic State Assignment zAll current methods are variants of this y1) Determine which states “attract” each other (weighted pairs) y2) Generate constraints on codes (which should be in same cube) y3) Place codes on Boolean cube so as to maximize constraints satisfied (weighted sum) zDifferent weights make sense depending on whether we are optimizing for two-level or multi-level forms zCan't consider all possible embeddings of state clusters in Boolean cube yHeuristics for ordering embedding yTo prune search for best embedding yExpand cube (more state bits) to satisfy more constraints

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 29 Output-Based Encoding zReuse outputs as state bits - use outputs to help distinguish states yWhy create new functions for state bits when output can serve as well yFits in nicely with synchronous Mealy implementations HG = ST’ H1’ H0’ F1 F0’ + ST H1 H0’ F1’ F0 HY = ST H1’ H0’ F1 F0’ + ST’ H1’ H0 F1 F0’ FG = ST H1’ H0 F1 F0’ + ST’ H1 H0’ F1’ F0’ HY = ST H1 H0’ F1’ F0’ + ST’ H1 H0’ F1’ F0 Output patterns are unique to states, we do not need ANY state bits – implement 5 functions (one for each output) instead of 7 (outputs plus 2 state bits) InputsPresent StateNext StateOutputs CTLTSSTHF 0––HGHG00010 –0–HGHG00010 11–HGHY10010 ––0HYHY00110 ––1HYFG10110 10–FGFG010 00 0––FGFY110 00 –1–FGFY110 00 ––0FYFY010 01 ––1FYHG110 01

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 30 Current State Assignment Approaches zFor tight encodings using close to the minimum number of state bits yBest of 10 random seems to be adequate (averages as well as heuristics) yHeuristic approaches are not even close to optimality yUsed in custom chip design zOne-hot encoding yEasy for small state machines yGenerates small equations with easy to estimate complexity yCommon in FPGAs and other programmable logic zOutput-based encoding yAd hoc - no tools yMost common approach taken by human designers yYields very small circuits for most FSMs

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CS 150 - Spring 2007 – Lec #21: Seq Logic Optimization - 31 Sequential Logic Implementation Summary zImplementation of sequential logic yState minimization yState assignment zImplications for programmable logic devices yWhen logic is expensive and FFs are scarce, optimization is highly desirable (e.g., gate logic, PLAs, etc.) yIn Xilinx devices, logic is bountiful (4 and 5 variable TTs) and FFs are many (2 per CLB), so optimization is not so crucial an issue as in other forms of programmable logic yThis makes sparse encodings like One-Hot worth considering

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