Presentation is loading. Please wait.

Presentation is loading. Please wait.

1 Lecture 21 State minimization via implication charts.

Similar presentations


Presentation on theme: "1 Lecture 21 State minimization via implication charts."— Presentation transcript:

1 1 Lecture 21 State minimization via implication charts

2 2 Row matching not optimal Two FSMs for odd parity checking

3 3 No rows match! Present State Next State Output X=0X=1 S0S0 S0S0 S1S1 0 S1S1 S1S1 S2S2 1 S2S2 S2S2 S1S1 0

4 4 FSM minimization Row matching  Easier to do by hand  Misses minimization opportunities Implication chart  Guaranteed to find the most reduced FSM  More complicated algorithm (but still relatively easy to write a program to do it)

5 5 Implication chart method Row matching will not work

6 6 Implication chart method Basic Idea: Assume that all states are grouped together and only split state pairs that must be split

7 7 Implication chart method 1.Draw a table with a box for every pair of states 2.Cross out boxes for pairs of states with different outputs 3.Fill rest of table with transition pairs  For each box and possible input, list pairs of destination states, one per source state 4.Repeat until no more boxes can be crossed out:  If box (Si,Sj) contains some transition pair Sk-Sl corresponding to an already crossed-out box then cross out box (Si,Sj) 5.Combine all pairs of states that are left

8 8 Step 1: Draw table of state pairs

9 9 Step 2: Consider the outputs

10 10 Step 3: Add transition pairs 0101 C-R

11 11 Step 3: Add transition pairs Transitivity: if states are combined then successor states must be combined 0101 C-R  if successor states cannot be combined then states cannot be combined

12 12 Step 4: Consider transitions

13 13 Final reduced FSM

14 14 Odd parity checker revisited Next State Present StateX=0X=1Output S0S0 S0S0 S1S1 0 S1S1 S1S1 S2S2 1 S2S2 S2S2 S1S1 0 S1 S2 S0S1 S0-S2 S1–S1

15 15 More complex minimization symbolic state transition table present next state output state S0S0S1S2S31 S1S0S3S1S40 S2S1S3S2S41 S3S1S0S4S50 S4S0S1S2S51 S5S1S4S0S50 inputs here S0 [1] S2 [1] S4 [1] S1 [0] S3 [0] S5 [0] 01

16 16 Implication chart S0-S1 S1-S3 S2-S2 S3-S4 S0-S0 S1-S1 S2-S2 S3-S5 S0-S1 S3-S0 S1-S4 S4-S5 S0-S1 S3-S4 S1-S0 S4-S5 S1-S0 S3-S1 S2-S2 S4-S5 S4-S0 S5-S5 S1-S1 S0-S4 S1 S2 S3 S4 S5 S0S1S2S3S4 present next state output state S0S0S1S2S31 S1S0S3S1S40 S2S1S3S2S41 S3S1S0S4S50 S4S0S1S2S51 S5S1S4S0S50

17 17 Minimized FSM minimized state table (S0==S4) (S3==S5) present next state output state S0'S0'S1S2S3'1 S1S0'S3'S1S3'0 S2S1S3'S2S0'1 S3'S1S0'S0'S3'0 present next state output state S0S0S1S2S31 S1S0S3S1S40 S2S1S3S2S41 S3S1S0S4S50 S4S0S1S2S51 S5S1S4S0S50 S0-S1 S1-S3 S2-S2 S3-S4 S0-S0 S1-S1 S2-S2 S3-S5 S0-S1 S3-S0 S1-S4 S4-S5 S0-S1 S3-S4 S1-S0 S4-S5 S1-S0 S3-S1 S2-S2 S4-S5 S4-S0 S5-S5 S1-S1 S0-S4 S1 S2 S3 S4 S5 S0S1S2S3S4

18 18 Minimizing not always good Two FSMs for 0  1 edge detection

19 19 Minimizing not always good InQ 1 Q 0 Q 1 + Q –10– – Q 1 + = In Q 0 Q 0 + = In Out = Q 1 ’ Q 0

20 20 Minimizing not always good InQ 1 Q 0 Q 1 + Q Q 1 + = Q 0 Q 0 + = In Out = Q 1 ’ Q 0

21 21 A little perspective These kinds of optimizations are what CAD (Computer Aided Design) / EDA (Electronic Design Automation) is all about The interesting problems are almost always computationally intractable to solve optimally People really care about the automation of the design of billion-transistor chips


Download ppt "1 Lecture 21 State minimization via implication charts."

Similar presentations


Ads by Google