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1 Progress and Challenges toward 100Gbps Ethernet Joel Goergen VP of Technology / Chief Scientist Abstract: This technical presentation will focus on the.

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Presentation on theme: "1 Progress and Challenges toward 100Gbps Ethernet Joel Goergen VP of Technology / Chief Scientist Abstract: This technical presentation will focus on the."— Presentation transcript:

1 1 Progress and Challenges toward 100Gbps Ethernet Joel Goergen VP of Technology / Chief Scientist Abstract: This technical presentation will focus on the progress and challenges for development of technology and standards for 100 GbE. Joel is an active contributor to IEEE802.3 and the Optical Internetworking Forum (OIF) standards process. Joel will discuss design methodology, enabling technologies, emerging specifications, and crucial considerations for performance and reliability for this next iteration of LAN/WAN technology.

2 2 Overview Network Standards Today Available Technology Today Feasible Technology for 2009 The Push for Standards within IEEE and OIF Anatomy of a 100Gbps or 160Gbps Solution Summary Backup Slides

3 3 Network Standards Today: The Basic Evolution Mb Mb GbE GbE 2010??? 100 GbE ???

4 4 Network Standards Today: The Basic Structure

5 5 Network Standards Today: The Desk top 1Gbps Ethernet –10/100/1000 Copper ports have been shipping with most desktop and laptop machines for a few years. –Fiber SMF/MMF IEEE a/b/g Wireless –Average useable bandwidth reaching 50Mbps

6 6 Network Standards Today: Clusters and Servers 1Gbps Ethernet –Copper 10Gbps Ethernet –Fiber –CX-4

7 7 Network Standards Today: Coming Soon 10Gbps LRM –Multi-mode fiber to 220meters. 10Gbps Base-T –100meters at more then 10Watts per port ??? –30meters short reach at 3Watts per port ??? 10Gbps Back Plane –1Gbps, 4x3.125Gbps, 1x10Gbps over 1meter improved fr-4 material.

8 8 Available Technology Today: System Implementation A+B Passive Copper Backplane A Fabric Line Card A A A A A A B B B B SPIx Front End SPIx Front End B Fabric 10G 1G 10G B B

9 9 Available Technology Today: System Implementation N+1 Front End Passive Copper Backplane 1st Switch Fabric Line Card L1 Ln+1 SPIx Front End SPIx Nth Switch Fabric N+1 Switch Fabric 10G 1G 10G L1 Ln Ln+1 Ln Ln+1

10 10 Available Technology Today: Zoom to Front-end Front End Passive Copper Backplane 1st Switch Fabric Line Card L1 Ln+1 SPIx Front End SPIx Nth Switch Fabric N+1 Switch Fabric 10G 1G 10G L1 Ln Ln+1 Ln Ln+1

11 11 Available Technology Today: Front-end Copper –RJ45 –RJ21 (mini … carries 6 ports) Fiber –XFP and variants (10Gbps) –SFP and variants (1Gbps) –XENPAK –LC/SC bulkhead for WAN modules

12 12 Available Technology Today: Front-end System Interfaces TBI –10bit Interface. Max speed 3.125Gbps. SPI-4 / SXI –System Protocol Interface. 16bit Interface. Max speed 11Gbps. SPI-5 –System Protocol Interface. 16bit Interface. Max speed 50Gbps. XFI –10Gbps Serial Interface.

13 13 Available Technology Today: Front-end Pipe Diameter 1Gbps –1Gbps doesn’t handle a lot of data anymore. –Non standard parallel also available based on OIF VSR. 10Gbps LAN/WAN or OC-192 –As port density increases, using 10Gbps as an upstream pipe will no longer be effective. 40Gbps OC-768 –Not effective port density in an asynchronous system. –Optics cost close to 30times 10Gbps Ethernet.

14 14 Available Technology Today: Front-end Distance Requirements x00 m (MMF) –SONET/SDH (Parallel): OIF VSR-4, VSR-5 –Ethernet:: 10GBASE-SR, 10GBASE-LX4, 10GBASE-LRM 2-10 km –SONET/SDH: OC-192/STM-64 SR-1/I-64.1, OC-768/STM-256 VSR2000-3R2/etc. –Ethernet: 10GBASE-LR ~40 km –SONET/SDH: OC-192/STM-64 IR-2/S-64.2, OC-768/STM-256 –Ethernet: 10GBASE-ER ~100 km –SONET/SDH: OC-192/STM-64 LR-2/L-64.2, OC-768/STM-256 –Ethernet: 10GBASE-ZR DWDM –OTN: ITU G.709 OTU-2, OTU-3 Assertion –Each of these applications must be solved for ultra high data rate interfaces.

15 15 Available Technology Today: Increasing Pipe Diameter 1Gbps LAN by 10links parallel 10Gbps LAN by x-links WDM 10Gbps LAN by x physical links Multiple OC-192 or OC-768 Channels

16 16 Available Technology Today: Zoom to Back Plane Front End Passive Copper Backplane 1st Switch Fabric Line Card L1 Ln+1 SPIx Front End SPIx Nth Switch Fabric N+1 Switch Fabric 10G 1G 10G L1 Ln Ln+1 Ln Ln+1

17 17 Available Technology Today: Back Plane Backplane SERDES Traces Line Cards -- GbE / 10 GbE RPMs SFMs Power Supplies Data Packet

18 18 Available Technology Today: Making a Back Plane Simple! It’s just multiple sheets of glass with copper traces and copper planes added for electrical connections. Reference: Isola

19 19 Available Technology Today: Back Plane Pipe Diameter 1.25Gbps –Used in systems with five to ten year old technology. 2.5Gbps/3.125Gbps –Used in systems with five year old or less technology. 5Gbps/6.25Gbps –Used within the last 12 months.

20 20 Available Technology Today: Increasing Pipe Diameter Can’t WDM copper 10.3Gbps/12.5Gbps –Not largely deployed at this time. Increasing the pipe diameter on a back plane with assigned slot pins can only be done by changing the glass construction.

21 21 Available Technology Today: Pipe Diameter is NOT Flexible Once the pipe is designed and built to a certain pipe speed, making the pipe faster is extremely difficult, if not impossible.

22 22 Available Technology Today: Gbits Density per Slot with Front End and Back Plane Interfaces Combined Year System IntroducedSlot density Gbps Gbps 2006/7 – in design now120Gbps Based on max back plane thickness of 300mils, 20TX and 20RX differential pipes.

23 23 Feasible Technology for 2009: Defining the Next Generation The overall network architecture for next generation ultra high (100, 120 and 160Gbps) data rate interfaces should be similar in concept to the successful network architecture deployed today using 10Gbps and 40Gbps interfaces. The internal node architectures for ultra high (100, 120 and 160Gbps) data rate interfaces should follow similar concepts in use for 10Gbps and 40Gbps interfaces. All new concepts need to be examined, but there are major advantages to scaling current methods with new technology.

24 24 Feasible Technology for 2009: Front-end Pipe Diameter 80Gbps … not enough Return On Investment 100Gbps 120Gbps 160Gbps Reasonable Channel Widths –10λ by Gbps –8λ by Gbps –4λ by Gbps –1λ by Gbps Suggest starting at an achievable channel width while pursuing a timeline to optimize the width in terms of density, power, feasibility, and cost - depending on optical interface application/reach.

25 25 Feasible Technology for 2009: Front-end Distance Requirements x00 m (MMF) –SONET/SDH: OC-3072/STM-1024 VSR –Ethernet: 100GBASE-S 2-10 km –SONET/SDH: OC-3072/STM-1024 SR –Ethernet: 100GBASE-L ~40 km –SONET/SDH: OC-3072/STM-1024 IR-2 –Ethernet: 100GBASE-E ~100 km –SONET/SDH: OC-3072/STM-1024 LR-2 –Ethernet: 100GBASE-Z DWDM (OTN) –SONET/SDH: Mapping of OC-3072/STM-1024 –Ethernet: Mapping of 100GBASE Assertion –These optical interfaces are defined today at the lower speeds. It is highly likely that industry will want these same interface specifications for the ultra high speeds. –Optical interfaces, with exception of VSR, are not typically defined in OIF. In order to specify the system level electrical interfaces, some idea of what industry will do with the optical interface has to be discussed. It is not the intent of this presentation to launch these optical interface efforts within OIF.

26 26 Feasible Technology for 2009: Front-end System Interfaces Reasonable Channel Widths (SPI-?) –16 lane by Gbps –10 lane by 10-16Gbps –8 lane by Gbps –5 lane by 20-32Gbps –4 lane by 25-40Gbps Port Density is impacted by channel width. Fewer lanes translates to higher Port Density and less power.

27 27 Feasible Technology for 2009: Back Plane Pipe Diameter Reasonable Channel Widths –16 lane by Gbps –10 lane by10-16Gbps –8 lane by Gbps –5 lane by 20-32Gbps –4 lane by 25-40Gbps Port Density is impacted by channel width. Fewer lanes translates to higher Port Density and less power.

28 28 Feasible Technology for 2009: Pipe Diameter is NOT Flexible New Back Plane designs will have to have pipes that can handle 20Gbps to 25Gbps.

29 29 Feasible Technology for 2009: Gbits Density per Slot with Front End and Back Plane Interfaces Combined Year System IntroducedSlot density Gbps Gbps 2006/7 – in design now120Gbps Gbps Based on max back plane thickness of 300mils, 20TX and 20RX differential pipes.

30 30 Feasible Technology for 2009: 100Gbps Options Bit rate shown above is based on 100Gbps. Scale the bit rate accordingly to achieve 160Gbps.

31 31 The Push for Standards: Interplay Between the OIF & IEEE OIF defines multi-source agreements within the Telecom Industry. –Optics and EDC for LAN/WAN –SERDES definition –Channel models and simulation tools IEEE 802 covers LAN/MAN Ethernet –802.1 and define Ethernet over copper cables, fiber cables, and back planes. –802.3 leverages efforts from OIF. Membership in both bodies is important for developing next generation standards.

32 32 The Push for Standards: OIF Force10 Labs introduced three efforts within OIF to drive 100Gbps to 160Gbps connectivity. –Two interfaces for interconnecting optics, ASICs, and backplanes. –A 25Gbps SERDES –Updates of design criteria to the Systems User Group

33 33 Case Study: Standards Process P802.3ah – Nov 2000 / Sept 2004 Call for Interest Study Group Task Force Working Group Ballot Sponsor Ballot Standards Board Approval Publication By a member of Open participation Members of Public ballot group RevCom & Stds Board IEEE Staff, project leaders 50% WG vote 75% WG PAR vote, 50% EC & Stds Bd 75% WG vote 75% WG ballot, EC approval 75% of ballot group 50% vote

34 34 10GBASE-LRM Innovations: TWDP Software reference equalizer Determines EDC penalty of transmitter Dual Launch Centre and MCP Maximum coverage for minimum EDC penalty Stress Channels Precursor, split and post-cursor Canonical tests for EDC Nov03 CFI Jan04 Study Group May04 Taskforce Nov03 TF Ballot Mar05 WG BAllot Dec05 Sponsor Ballot Mid-06 Standard Time line dBm 0.4 dB: Fiber attenuation 0.3 dB: RIN dBm 4.4 dB: TP3 TWDP and connector 99% confidence level 0.2 dB: Modal noise Optical Power Budget (OMA) 0.9 dB: Unallocated power Launch power (min) Required effective receiver sensitivity 0.5 dB: Transmitter implementation Case Study: Standards Process 10GBASE_LRM: 2003 / 2006 Reference: David Cunningham – Avago Technologies

35 35 Case Study: Standards Process 10GBASE_LRM - 4.5dBm Launch power minimum Connector losses = 1.5dB Fiber attenuation = 0.4dB Power budget starting at TP2 Interaction penalty = 0.1dB Ideal EDC power penalty, PIE_D = 4.2dB dBm Specified optical power levels (OMA) Effective maximum unstressed 10GBASE-LRM receiver sensitivity dBm Optical input to receiver (TP3) compliance test allocation Attenuation (2 dB) Noise (0.5 dB) Dispersion (4.2 dB) RIN = 0.3 dB Modal noise = 0.2 dB TWDP and connector loss at 99 th percentile (4.4 dB) Fiber attenuation = 0.4 dB RIN = 0.3 dB Modal noise = 0.2 dB Transmit implementation allowance = 0.5 dB Unallocated margin 0.9 dB Stressed receiver sensitivity Reference: David Cunningham – Avago Technologies

36 36 Case Study: Standards Process 10GBASE_T: 2002 / 2006 Techno-babble –64B/65B encoding (similar to 10GBASE-R) –LDPC(1723,2048) framing –DSQ128 constellation mapping (PAM16 with ½ the code points removed) –Tomlinson-Harshima precoder Reach –Cat 6 up to 55 m with the caveat of meeting TIA TSB-155 –Cat 6A up to 100 m –Cat 7 up to 100 m –Cat 5 and 5e are not specified Power –Estimates for worst case range from 10 to 15 W –Short reach mode (30 m) has a target of sub 4 W

37 37 Case Study: Standards Process 10GBASE_T Noise and EMI –Alien crosstalk has the biggest impact on UTP cabling –Screened and/or shielded cabling has better performance Power –Strong preference for copper technologies, even though higher power –Short reach and better performance cable reduce power requirement Timeline –The standard is coming… products in the market end of `06, early `07 JULNOVMAR2004JULNOVMAR2005JULNOVMAR2006JUL Tutorial & CFI D Ballot D2.0STD SponsorBallot NOV2002MAR2003 PAR Task Force review D3.0 1 st Technical Presentation

38 38 Birth of A Standard It Takes About 5 Years Ideas from industry Feasibility and research Call for Interest (CFI) – 100 GbE EFFORT IS HERE Marketing / Sales potential, technical feasibility Study Group Work Group Drafts Final member vote

39 39 The Push for Standards: IEEE Force10 introduces a Call for Interest (CFI) in July 2006 IEEE802 with Tyco Electronics. –Meetings will be held in the coming months to determine the CFI and the efforts required. –We target July 2006 because of resources within IEEE. –Joel Goergen and John D’Ambrosia will chair the CFI effort. The anchor team is composed of key contributors from Force10, Tyco, Intel, Quake, and Cisco. It has since broadened to include over 30 companies.

40 40 The Ethernet Alliance Promoting All Ethernet IEEE Work Key IEEE 802 Ethernet projects include –100 GbE –Backplane –10 GbE LRM / MMF –10 G Base-T Force10 is on the BoD, principle member 20 companies at launch –Sun, Intel, Foundry, Broadcam... –Now approaching 40 companies Launch January 10, 2006 Opportunity for customers to speak on behalf of 100 GbE Ethernet

41 41 Anatomy of a 100Gbps Solution: Architectural Disclaimers There Are Many Ways to Implement a system –This section covers two basic types. –Issues facing 100Gbps ports are addressed in basic form. Channel Performance or ‘Pipe Capacity’ is difficult to measure Two Popular Chassis Heights –24in to 34in Height (2 or 3 Per Rack) –10in to 14in Height (5 to 8 Per Rack)

42 42 Anatomy of a 100Gbps Solution: What is a SERDES? Device that attaches to the ‘channel’ or ‘pipe’ Transmitter: –Parallel to serial –Tap values –Pre-emphasis Receiver: –Serial to Parallel –Clock and Data Recovery –DFE –Circuits are very sensitive to power noise and low Signal to Noise Ration (SNR) Reference: Altera

43 43 Anatomy of a 100Gbps Solution: Interfaces that use SERDES TBI –10bit Interface. Max speed 3.125Gbps across all 10 lanes. This is a parallel interface that does not use SERDES technology. SPI-4 / SXI –System Protocol Interface. 16bit Interface. Max speed 11Gbps. This is a parallel interface that does not use SERDES technology. SPI-5 –System Protocol Interface. 16bit Interface. Max speed 50Gbps. This uses 16 SERDES interfaces at speeds up to 3.125Gbps. XFI –10Gbps Serial Interface. This uses 1 SERDES at Gbps. XAUI –10Gbps 4 lane Interface. This uses 4 SERDES devices at 3.125Gbps each.

44 44 Anatomy of a 100Gbps Solution: Power Noise thought … Line Card SERDES Noise Limits –Analog target 60mVpp ripple –Digital target 150mVpp ripple Fabric SERDES Noise Limits –Analog target 30mVpp ripple –Digital target 100mVpp ripple 100Gbps interfaces won’t operate well if these limits can not be meet.

45 45 Anatomy of a 100Gbps Solution: Memory Selection Advanced Content-Addressable Memory (CAM) –Goal: Less power per search –Goal: 4 times more performance –Goal: Enhanced flexible table management schemes Memories –Replacing SRAMs with DRAMs when performance allows to conserve cost –Quad Data Rate III SRAMs for speed –SERDES based DRAMs for buffer memory Need to drive JEDEC for serial memories that can be easily implemented in a communication system. –The industry is going to have to work harder to get high speed memories for Network Processing in order to reduce latency. Memory chips are usually the last thought! This will need to change for 100Gbps sustained performance.

46 46 Anatomy of a 100Gbps Solution: ASIC Selection High Speed Interfaces –Interfaces to MACs, Backplane, Buffer Memory are all SERDES based. SERDES all the way. Higher gate counts with internal memories target to 6.25 SERDES; higher speeds difficult to design in this environment. –SERDES used to replace parallel busing for reduced pin and gate count Smaller Process Geometry –Definitely 0.09 micron or lower –More gates(100% more gates over 0.13 micron process) –Better performance(25% better performance) –Lower power(1/2 the 0.13 micron process power) –Use power optimized libraries Hierarchical Placement and Layout of the Chips –Flat placement is no longer a viable option To achieve cost control, ASIC SERDES speed is limited to 6.25Gbps in high density applications.

47 47 Anatomy of a 100Gbps Solution: N+1 Redundant Fabric - BP Front End Passive Copper Backplane 1st Switch Fabric Line Card L1 Ln+1 SPIx Front End SPIx Nth Switch Fabric N+1 Switch Fabric L1 Ln Ln+1 Ln Ln+1

48 48 Passive Copper Midplane Anatomy of a 100Gbps Solution: N+1 Redundant Fabric – MP 1st Switch Fabric Line Card L1 SPIx Front End SPIx Front End SPIx Ln+1 Nth Switch Fabric N+1 Switch Fabric L1 Ln Ln+1 Ln Ln+1

49 49 Anatomy of a 100Gbps Solution: N+1 High Speed Channel Routing 1st Switch Fabric Nth Switch Fabric N+1 Switch Fabric 2nd Switch Fabric Line Card

50 50 Passive Copper Backplane Anatomy of a 100Gbps Solution: A/B Redundant Fabric - BP A Fabric Line Card A A A A A A B B B B B B SPIx Front End SPIx Front End B Fabric

51 51 Passive Copper Midplane Anatomy of a 100Gbps Solution: A/B Redundant Fabric – MP A Fabric Line Card A A A A B Fabric B B B B B B SPIx Front End SPIx Front End SPIx A A

52 52 Anatomy of a 100Gbps Solution: A/B High Speed Channel Routing B Switch Fabric Line Card A Switch Fabric Line Card Line Card Line Card

53 53 Anatomy of a 100Gbps Solution: A Quick Thought ….. Looking at both Routing and Connector Complexity designed into the differential signaling …. –Best Case: N+1 Fabric in a Back Plane. –Worst Case: A/B Fabric in a Mid Plane. All implementations need to be examined for best possible performance over all deployed network interfaces. Manufacturability and channel (Pipe) noise are two of the bigger factors.

54 54 Anatomy of a 100Gbps Solution: Determine Trace Lengths After careful review of possible Line Card, Switch Fabric, and Back Plane Architectural blocks, determine the range of trace lengths that exist between a SERDES transmitter and a SERDES receiver. 30 inches or.75meters total should do it. Several factors stem from trace length. –Band Width –Reflections from via and or thru-holes –Circuit board material –BER –Coding Keep in mind that the goal is to target one or both basic chassis dimensions.

55 55 Anatomy of a 100Gbps Solution: Channel Model Description A “Channel” or “Pipe” is a high speed single- ended or differential signal connecting the SERDES transmitter to the SERDES receiver. The context of “Channel” or “Pipe” from this point is considered differential. Develop a channel model based on the implications of Architectural choices and trace lengths. –Identifies a clean launch route to a BGA device. –Identifies design constraints and concerns. –Includes practical recommendations. –Identifies channel Bandwidth.

56 56 Anatomy of a 100Gbps Solution: Channel Simulation Model XMTR FR4+ CONN PLUG CONN JACK FR4+ CONN JACK CONN PLUG FR4+ RCV FILTER RCV SLICER Transmitter Receiver TP1TP4 Channel DC block TP2 and TP3 not used FR4+ TP5 Informative equivalent cap circuit Back Plane Line Card: Receiver

57 57 Anatomy of a 100Gbps Solution: Channel: Back Plane Shows signal trace connecting pins on separate connectors across a back plane.

58 58 Anatomy of a 100Gbps Solution: Channel: Line Card Receiver Shows a signal trace connecting the back plane to a SERDES in a Ball Grid Array (BGA) package.

59 59 Channel Model Definition: Back Plane Band Width 2Ghz to 3Ghz Band Width –Supports 2.5Gps NRZ – 8B10B 2Ghz to 4Ghz Band Width –Supports 3.125Gps NRZ – 8B10B 2Ghz to 5Ghz Band Width (4Ghz low FEXT) –Supports 6.25Gps PAM4 –Supports 3.125Gps NRZ – 8B10B or Scrambling 2Ghz to 6.5Ghz –Supports 6.25Gps NRZ – 8B10B –Limited Scrambling Algorithms 2Ghz to 7.5Ghz –Supports 12Gps –Limited Scrambling Algorithms 2Ghz to 9Ghz –Supports 25Ghz multi-level How do we Evaluate the signal speed that can be placed on a channel?

60 60 Channel Model Definition – IEEE 802.3ae XAUI Limit b1 = 6.5e-6 b2 = 2.0e-10 b3 = 3.30e-20 SDD21 = -20*log10(e)*(b1*sqrt(f) + b2*f + b3*f^2) f = 50Mhz to 15000Mhz

61 61 Channel Model Definition – IEEE 802.3ap A(min) b1 = 2.25e-5 b2 = 1.20e-10 b3 = 3.50e-20 b4 = 1.25e-30 SDD21 = -20*log10(e)*(b1*sqrt(f) + b2*f + b3*f^2 - b4*f^3) f = 50Mhz to 15000Mhz

62 62 Anatomy of a 100Gbps Solution: Channel Model Limit Lines

63 63 Anatomy of a 100Gbps Solution: Comments on Limit Lines IEEE802.3ae XAUI is a 5year old channel model limit line. IEEE P802.3ap channel model limit is based on mathematical representation of improved FR-4 material properties and closely matches “real life” channels. This type of modeling will be essential for 100Gbps interfaces. A real channel is shown with typical design violations common in the days of XAUI. Attention to specific design techniques in the channel launch conditions can eliminate the violation to the defined channel limits.

64 64 Anatomy of a 100Gbps Solution: Receiver Conditions – Case 1 TP4 TP5 Informative 13mil Drill 24mil 24milx32mil 24mil 21mil BGA6 12mil AG trace to BP trace trace dogbone 34mil Anti Pad

65 65 Anatomy of a 100Gbps Solution: Constraints & Concerns – Case 1 Poor Signal Integrity – SDD11/22/21 Standard Cad Approach Easiest / Lowest Cost to Implement Approach will not have the required performance for SERDES implementations used in 100Gbps interfaces.

66 66 Anatomy of a 100Gbps Solution: Receiver Conditions– Case 4 TP4 TP5 Informative 13mil Drill 24mil 24milx32mil 21mil BGA6 12mil AG trace to BP trace trace dogbone 34mil Anti Pad

67 67 Anatomy of a 100Gbps Solution: Constraints & Concerns – Case 4 Ideal Signal Integrity –Eliminates two VIAS –Increases pad impedance to reduce SDD11/22 High speed BGA pins must reside on the outer pin rows Crosstalk to traces routed under the open ground pad is an issue for both the BGA and the Capacitor footprint Requires 50mil pitch BGA packaging to avoid ground plane isolation on the ground layer under the BGA pads Potential to require additional routing layer

68 68 Available Technology Today: Remember this Slide ? Circuit board material is just multiple sheets of glass with copper traces and copper planes added for electrical connections. Reference: Isola

69 69 Anatomy of a 100Gbps Solution: Channel Design Considerations Circuit Board Material Selection is Based on the Following: –Temperature and Humidity effects on Df (Dissipation Factor) and Dk (Dielectric Constant) –Required mounting holes for mother-card mounting, shock and vibration –Required number of times a chip or connector can be replaced –Required number of times a pin can be replaced on a back plane –Aspect ratio (Drilled hole size to board thickness) –Power plane copper weight –Coding / Signaling scheme

70 70 Anatomy of a 100Gbps Solution: Materials in Perspective Graph provided by Zhi Wong

71 71 “Improved FR-4” in Reference to IEEE P802.3ap Improved FR-4 (Mid Resolution Signal Integrity): –100Mhz: Dk ≤ 3.60; Df ≤.0092 –1Ghz: Dk ≤ 3.60; Df ≤.0092 –2Ghz: Dk ≤ 3.50; Df ≤.0115 –5Ghz: Dk ≤ 3.50; Df ≤.0115 –10Ghz: Dk ≤ 3.40; Df ≤.0125 –20Ghz: Dk ≤ 3.20; Df ≤.0140 Temperature and Humidity Tolerance (0-55degC, 10-90% non-condensing): –Dk:+/-.04 –Df: +/-.001 Resin Tolerance (standard +/-2%): –Dk:+/-.02 –Df: +/-.0005

72 72 Anatomy of a 100Gbps Solution: Channel or Pipe Considerations Channel Constraints Include the Following: –Return Loss –Thru-hole reflections –Routing reflections –Insertion Loss based on material category –Insertion Loss based on length to first reflection point –Define coding and baud rate based on material category –Connector hole crosstalk –Trace to trace crosstalk –DC blocking Capacitor at the SERDES to avoid shorting DC between cards. –Temperature and Humidity losses/expectations based on material category

73 73 Channel Model Starting Point: Materials in Perspective Graph provided by Zhi Wong Target Area

74 74 Channel Model Starting Point: Real Channels

75 75 Channel Model Starting Point: Equation b1 = 1.25e-5 b2 = 1.20e-10 b3 = 2.50e-20 b4 = 0.95e-30 SDD21 = -20*log10(e)*(b1*sqrt(f) + b2*f + b3*f^2 - b4*f^3) f = 50Mhz to 15000Mhz

76 76 Anatomy of a 100Gbps Solution: Channel Design Considerations Channel BER –Data transmitted across the back plane channel is usually done in a frame with header and payload –The frame size can be anywhere from a few hundred bytes to 16Kbytes, typical –A typical frame contains many PHY-layer packets –BER of 10E-12 will result in a frame error of 10E-7 or less, depending on distribution –That is a lot of frame loss

77 77 Anatomy of a 100Gbps Solution: Channel Design Considerations Channel BER –Customers want to see a frame loss of zero –Systems architects want to see a frame loss of zero –Zero error is difficult to test and verify … none of us will live that long –The BER goal should be 10E-15 –It can be tested and verified at the system design level –Simulate to 10E-17 –Any frame loss beyond that will have minimal effect on current packet handling/processing algorithms –Current SERDES do not support this. Effective 10E-15 is obtained by both power noise control and channel model loss This will be tough to get through, but without this tight requirement, 100Gbps interfaces will need to run faster by 3% to 7%. Or worse, pay a latency penalty for using FEC or DFE.

78 78 Anatomy of a 100Gbps Solution: Remember Interface Speeds … Reasonable Channel Widths for 100Gbps: –16 lane by 6.25Gbps *BEST –10 lane by 10Gbps –8 lane by 12.5Gbps –5 lane by 20Gbps –4 lane by 25Gbps *BEST

79 79 Anatomy of a 100Gbps Solution: Channel Signaling Thoughts Channel Signaling: –NRZ –In general, breaks down after 12.5Gbps –8B10B is not going to work at 25Gbps –64B66B is not going to work at 25Gbps –Scrambling is not going to work at 25Gbps –Duo-Binary –Demonstrated to 33Gbps –PAM4 or PAMx –Demonstrated to 33Gbps

80 80 Anatomy of a 100Gbps Solution: Designing for EMI Compatibility Treat each slot as a unique chamber –Shielding Effectiveness determines the maximum number of 1GigE ports, 10GigE ports, or 100GigE ports before saturating emissions requirements. –Requires top and bottom seal using honeycomb Seal the back plane / mid plane –Cross-hatch chassis ground –Chassis ground edge guard and not edge plate –Digital ground sandwich for all signal layers Provide carrier mating surface EMI follows wave equations. Signaling spectrum must be considered.

81 81 Anatomy of a 100Gbps Solution: Power Design Power Routing Architecture from Inputs to All Cards –Bus bar –Power board –Cabling harness –Distribution through the back plane / mid plane using copper foil Design the Input Filter for Maximum Insertion Loss and Return Loss –Protects your own equipment –Protects all equipment on the power circuit Design Current Flow Paths for 15DegC Max Rise, 5 DegC Typical Design all Distribution Thru-holes to Support 200% Loading at 60DegC –Provides for the case when the incorrect drill size is selected in the drilling machine and escapes computer comparison. Unlikely case but required in carrier applications Power Follows Ohm’s Law. It Can Not Be Increased without Major Changes or Serious Thermal Concerns

82 82 Summary Industry has been successful scaling speed since 10Mbps in The efforts in 1GigE and 10GigE have taught us many aspects of interfaces and interface technology. 100Gbps and 160Gbps success will depend on useable chip and optics interfaces. Significant effort is underway in both IEEE and OIF to define and invent interface to support the next generation speeds. Systems designers will need to address many new issues to support 100Gbps port densities of 56 or more per box.

83 83 Thank You

84 84 Backup Slides The following slides provide additional detail to support information provided within the base presentation.

85 85 Acronym Cheat Sheet CDR – Clock and Data Recovery CEI – Common Electrical Interface CGND / DGND – Chassis Ground / Digital Ground EDC – Electronic Dispersion Compensation MAC – Media Access Control MDNEXT / MDFEXT – Multi Disturber Near / Far End Cross Talk MSA – Multi Source Agreement NEXT / FEXT – Near / Far End Cross Talk OIF – Optical Internetworking Forum PLL - Physical Link Layer SERDES – Serialize / De-serialize SFI – System Framer Interface SMF / MMF – Single Mode Fiber / Multi Mode Fiber XAUI – 10Gig Attachment Unit Interface

86 86 PMD Anatomy of a 100Gbps Solution: Basic Line Card Architecture PHY, Framer PHY, Framer Protocol Stacks, Applications APPs Non “Wire Speed” µP Non “Wire Speed” µP Network Processor Network Processor Fabric Interface Fabric Interface

87 87 Anatomy of a 100Gbps Solution: Basic Line Card Architecture 1 Architecture: –Long trace lengths. –Poor power noise control means worse than... –Analog target 60mVpp ripple –Digital target 150mVpp ripple –Poor SERDES to connector signal flow will maximize ground noise. –This layout is not a good choice for 100Gbps. Media Forwarding Engine Backplane Optical or Copper Media Reserved for Power Network Processor SERDES

88 88 Anatomy of a 100Gbps Solution: Basic Line Card Architecture 2 Architecture: –Clean trace routing. –Good power noise control means better than... –Analog target 60mVpp ripple –Digital target 150mVpp ripple –Excellent SERDES to connector signal flow to minimize ground noise. –Best choice for 100Gbps systems. Media Forwarding Engine Backplane Optical or Copper Media Reserved for Power Network Processor S E R D E S S E R D E S

89 89 Midplane Media Forwarding Engine Optical or Copper Media Reserved for Power Network Processor SERDESSERDES Anatomy of a 100Gbps Solution: Basic Line Card Architecture 3 Architecture: –Clean trace routing. –Good power noise control means better than... –Analog target 60mVpp ripple –Digital target 150mVpp ripple –Difficult SERDES to connector signal flow because of Mid Plane. –This layout is not a good choice for 100Gbps.

90 90 Line Card Interface Line Card Interface Anatomy of a 100Gbps Solution: Basic Switch Fabric Architecture Non “Wire Speed” µP Non “Wire Speed” µP Digital or Analog X bar Digital or Analog X bar Line Card Interface Line Card Interface

91 91 Anatomy of a 100Gbps Solution: Basic Switch Fabric Architecture 1 Architecture: –Long trace lengths. –Poor power noise control means worse than... –Analog target 30mVpp ripple –Digital target 100mVpp ripple –Poor SERDES to connector signal flow will maximize ground noise. –This layout is not a good choice for 100Gbps. Reserved for Power Digital Cross Bar SERDES

92 92 Anatomy of a 100Gbps Solution: Basic Switch Fabric Architecture 2 Architecture: –Clean trace routing. –Good power noise control means better than... –Analog target 30mVpp ripple –Digital target 100mVpp ripple –Excellent SERDES to connector signal flow to minimize ground noise. Digital Cross Bar SERDESSERDES SERDESSERDES Reserved for Power

93 93 Analog Cross Bar Reserved for Power Anatomy of a 100Gbps Solution: Basic Switch Fabric Architecture 3 Architecture: –Clean trace routing. –Good power noise control means better than... –Analog target 30mVpp ripple –Digital target 100mVpp ripple –Excellent SERDES to connector signal flow to minimize ground noise. –True Analog Fabric is not used anymore.

94 94 Anatomy of a 100Gbps Solution: Back Plane or Mid Plane Redundancy –N+1 Fabric –A / B Fabric Connections –Back Plane –Mid Plane

95 95 Anatomy of a 100Gbps Solution: Trace Length Combinations - Max 24in to 34in height (2 or 3 per rack)

96 96 Anatomy of a 100Gbps Solution: Trace Length Combinations - Min 24in to 34in height (2 or 3 per rack)

97 97 Anatomy of a 100Gbps Solution: Trace Length Combinations - Max 10in to 14in height (5 to 8 per rack)

98 98 Anatomy of a 100Gbps Solution: Trace Length Combinations - Min 10in to 14in height (5 to 8 per rack)

99 99 Anatomy of a 100Gbps Solution: Receiver Conditions– Case 2 TP4 TP5 Informative 13mil Drill 24mil 24milx32mil 24mil 21mil BGA6 12mil AG trace to BP trace trace dogbone 34mil Anti Pad

100 100 Anatomy of a 100Gbps Solution: Constraints & Concerns – Case 2 Crosstalk to Traces Routed Under the Open Ground Pad is an Issue Allows Good Pin Escape from the BGA Poor Signal Integrity - Has High SDD11/22/21 at the BGA Potential to Require Additional Routing Layer Approach will not have the required performance for SERDES implementations used in 100Gbps interfaces.

101 101 Anatomy of a 100Gbps Solution: Receiver Conditions– Case 3 TP4 TP5 Informative 13mil Drill 24mil 24milx32mil 24mil 21mil BGA6 12mil AG trace to BP trace trace dogbone 34mil Anti Pad

102 102 Anatomy of a 100Gbps Solution: Constraints & Concerns – Case 3 Allows for Inner High Speed Pad Usage within the BGA Medium Poor Signal Integrity – SDD11/22/21. Has the Extra VIAS to Content with in the Break Out –Increases pad impedance to reduce SDD11/22 Crosstalk to Traces Routed Under the Open Ground Pad is an Issue for Both the BGA and the Capacitor Footprint Allows Good Pin Escape from the BGA Potential to Require Additional Routing Layer Requires 50mil Pitch BGA Packaging to Avoid Ground Plane Isolation on the Ground Layer Under the BGA Pads

103 103 Anatomy of a 100Gbps Solution: Stack-up Detail

104 104 Requirements to Consider when Increasing Channel Speed Signaling Scheme vs Available Bandwidth NEXT/FEXT Margins Average Power Noise as Seen by the Receive Slicing Circuit and the PLL Insertion Loss (SDD21) Limits


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