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Clock distributions (v.9a)1 CENG3480_B1 Digital System Clock Reference: Chapter11 of High speed digital design, by Johnson and Graham.

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Presentation on theme: "Clock distributions (v.9a)1 CENG3480_B1 Digital System Clock Reference: Chapter11 of High speed digital design, by Johnson and Graham."— Presentation transcript:

1 Clock distributions (v.9a)1 CENG3480_B1 Digital System Clock Reference: Chapter11 of High speed digital design, by Johnson and Graham

2 Clock distributions (v.9a)2 Setup time and Time margin §Setup time: The time that the input data must be stable before the clock transition of the system occurs. §Timing margin measures the slack, or excess time, remaining in each clock cycle l Protects your circuit against signal cross-talk, miscalculation of logic delays, and later minor changes in the layout. l Depends on both time delay of logic paths and clock interval.

3 Clock distributions (v.9a)3 Example to show the importance of time margin §A 2-bit ring counter §Initially A,B =0 ; A=001100110 §What is B? A B Ans: 011001100

4 Clock distributions (v.9a)4 A 2-bit ring counter example (Cont’d) §The result is ok when the clock is slow. §But we may have problems when the clock is too fast. (see next page)

5 Clock distributions (v.9a)5 § May cause problem if T CLK is too short

6 Clock distributions (v.9a)6 Exercise B4.1 §Given: l CLK 1 =CLK 2 =20MHz, l FF clock-to-Q output delay=8ns; l setup time for FF is 5ns; l Gate delay G is 10ns; l Q1 Q2 are 0 initially. §Questions: l Find time margin. l How many delay G gates can you insert between A and B without creating error? A B

7 Clock distributions (v.9a)7 §The clock does not reach at FF1, FF2 at the same time §E.g. Clock skew =(T C1,max - T C2,min ) =1 ns, §a positive skew when T C2,min happens earlier than T C1,max, FCLK0 cannot be too high. Skew (T C1,max - T C2,min ) A positive skew TCLK1 TCLK2 delay1 Source clock:CLK0 delay2 T C1,max = latest T C1 arrival time T C2,min = earliest T C2 arrival time CLK0 Set t=0 here Clock Skew

8 Clock distributions (v.9a)8 Clock skew § FF1 FF2 Clock source CLK1 CLK2 Skew (T C1,max -T C2, min ) Time t=0 T c2 T c1 T clock T setup T FF +T G

9 Clock distributions (v.9a)9 Clock skew (at FF1) §Due to the problem when the synchronous clock does not arrive at various components at the same time. §The latest possible arrival time for a pulse coming through gate G is T slow = T C1,max + T FF,max + T G,max l T slow = slowest arrival for pulse from G l T C1,max =Max. delay of path C 1 l T FF,max =Max. delay, clock to Q of FF1 l T G,max =Max. delay of G, including trace delay

10 Clock distributions (v.9a)10 Clock Skew ( at FF2, the next cycle) §The arrival time required by FF2 is T required = T CLK + T C2,min - T setup l T required = elapsed time by which data from G must arrive l T CLK =interval between clocks; clock period l T C2,min =Minimum delay of path C 2 l T setup =worst-case setup time required by FF2, data at D1 must arrive at least T setup before CLK 2

11 Clock distributions (v.9a)11 Clock Skew ( combining delay & setup requirements) §Data from G must arrive before T required to properly set FF2. So, l T required – T slow > 0, hence T required > T slow, therefore l T CLK + T C2,min - T setup > T C1,max + T FF,max + T G,max l T CLK > T FF,max + T G,max + T setup + (T C1,max - T C2,min ) + T some_margin §Example: assuming l T FF,max = 6ns l Delay between Flip-flops, T G,max + T setup = 5ns + 3ns = 8ns l clock skew =(T C1,max -T C2,min ) =1ns, a positive skew when T C2,min happens earlier than T C1,max. l Timing margin T some_margin = 4ns (make sure the circuit is reliable) l Total = 18ns ==> F max = 55.5MHz l Use clock frequency =55MHz would be safe.

12 Clock distributions (v.9a)12 Exercise: B4.2 §Given: l T FF,max = 7ns l T G,max = 5ns l T setup =4ns l Timing margin T margin =3ns l F CLK =40MHz §What is the biggest time skew allowed?

13 Clock distributions (v.9a)13 Strategies to reduce clock skew §Two main strategies: 1.Locate all clock inputs close together; but it is difficult to implement in a large circuit. 2.Drive them from the same source & balance the delays §Due to physical limitation, strategy 2 is often used 1.Spider-leg distribution network l use a power driver to drive N outputs. l Use load (R) termination to reduce reflection if the traces are long (distributed circuit). Total load =R/N. l E.g. line impedance=75 , N=3, total load=25 . l Two or more driver outputs in parallel may be needed. 2.Clock distribution tree.

14 Clock distributions (v.9a)14 Spider leg Distribution Network §

15 Clock distributions (v.9a)15 Clock distribution tree §

16 Clock distributions (v.9a)16 Delay adjustment §The simplest clock adjustment is fixed delay. §Fixed delay: l Delay line by transmission line: short delays 0.1-5ns, 10% variation, accurate. l Gate delays 0.1-20ns, 300% variation, not accurate. l Lumped-circuit delay (RC) Figure 11.10: 0.1->1000ns, variation 5-20%, accurate. §Adjustable delays l Delay line directly printed on PCB; delay may vary with temperature l Insert a RC circuit between two buffers

17 Clock distributions (v.9a)17 Selectable delay adjustment (using jumper)

18 Clock distributions (v.9a)18 Selectable delay adjustment (using jumper) §Jumper block will have bigger Capacitance §Use direct solder is better by more difficult to tune

19 Clock distributions (v.9a)19 Low Impedance Clock Distribution Line §Three means to reduce reflection pulse heights l Slow the rise & fall time of the driver l Lower the capacitance of each tap l Lower the characteristic impedance of the clock distribution line §Must also try to minimize the parasitic capacitance of the connector and PCB

20 Clock distributions (v.9a)20 Differential Distribution §Can survive tougher noise environment l Better signal size (lower amplitude: half) l Differential Balance §ECL signal system is better than TTL

21 Clock distributions (v.9a)21 Clock Signal Duty Cycle §Ideal duty cycle: 50% §Falling edge of an ideal clock signal bisects successive rising edge §Average DC value lies halfway between Hi & Lo states §Keeping symmetry is difficult because asymmetry response to rising and falling edge l Different propagation delays T LH & T HL §Long chain of identical gates will distort the pulse width, positive pulse may emerge shorter (and vice versa) §Two clever tricks: l Inverts the clock signal at every stage (balance the distortion) l Use analog circuit to reshape the waveform

22 Clock distributions (v.9a)22 Analogue circuit to reshape the clock §Tuning is difficult

23 Clock distributions (v.9a)23 Cancelling Parasitic Capacitance §When new device is added to a multi-drop line, the parasitic capacitance may cause clock phase shift (a function of the parasitic Capacitance) §Use a negative reactance to cancel the effect l works at a particular frequency only

24 Clock distributions (v.9a)24 Clock Generators (Oscillators) §Seldom design our own §Comes in hermetically sealed package l A thick film hybrid circuit on a substrate §More important to understand the requirements

25 Clock distributions (v.9a)25 Frequency Specifications §Frequency (Hertz, KHz, MHz, GHz) l Nominal operating frequency or centre frequency l Higher frequency is synthesis by filtering and enhancing harmonics of the crystal’s fundamental operating frequency §Stability l Consolidates variations due to temperature, manufacturing processes, operating voltage and aging l In parts per million (ppm); one-hundred ppm = 0.01 % §Aging l In ppm/year l Younger crystal ages faster §Voltage sensitivity

26 Clock distributions (v.9a)26 Allowed Operating Conditions §Temperature l Typically 0 – 70 o C l Cause Frequency change l Temperature drift is not linear §Input voltage l Like Vcc spec. for IC §Shock l Refers to mechanical (not electrical) shock l In units of G’s l Apply shock tests in both polarities along all three geometric axes §Vibration l Similar to shock, violently shakes the oscillator l Shock & vibration tests are essential to military or similar products §Humidity l Hermetically sealed package can easily work at any condition

27 Clock distributions (v.9a)27 Electrical Parameters §Output type l TTL, CMOS or ECL (10K or 100K) outputs §Maximum loading l Excess load may cause drift §Duty Cycle l More difficult to guarantee at higher frequency §Rise and fall times l Common practice: 10-90% are given in ns §Input current l In milliamps l A function of the Frequency; higher the frequency, more energy is required

28 Clock distributions (v.9a)28 Mechanical Configuration §DIP §Half DIP §Surface mount Manufacturing Issues §Solderability §Cleaning §Package leak rate

29 Clock distributions (v.9a)29 Reliability §Functional screening (how many did manufacturer test) §Aging at accelerated temperature Bells and Whistles §Differential outputs §Enable §Voltage controlled oscillator (adjust frequency electronically) §Tuning

30 Clock distributions (v.9a)30 Other Issues §Clock Jitter l Clock oscillator contains a high frequency amplifier that may resonate l This high frequency signal may appear as noise and appears at the output in the form of clock jitter (superimpose of base signal and higher frequency components) l May cause malfunction l Can use measuring technique and feedback system to control the effect

31 Clock distributions (v.9a)31 §Need to control Power supply stability l Supply variation will affect the frequency and will appear as noise §Laying clock signal lines also need special attention l Cause lots of noise (cross talk due to high frequency) l Must try to specify, demand special treatment and lay out the clock distribution network first l Use thicker line or isolation grid to make bigger separation from other signals l Use a separate layer

32 Clock distributions (v.9a)32 Answer for B4.1 §Clock cycle is (T) 1/20Mhz = 50 ns §Time margin = T- clock_to_Q+ setup_time - delay_G § = 50ns – 8ns-5ns-10ns=27ns §Since each delay is 10ns, so you may add 2 more (totally 3 between A and B).

33 Clock distributions (v.9a)33 Answer: B4.2 § T CLK > T FF,max + T G,max + T setup + (T C1,max -T C2,min ) +T margin § T FF,max = 7ns § T G,max = 5ns; T setup =4ns § Timing margin T margin =3ns § F CLK =40MHz => T CLK =25ns § Max. Time skew (T C1,max -T C2,min )> T CLK -(T FF,max + T G,max +T setup +T margin ) =25ns- (7ns+5ns+4ns+3ns)= 6ns.

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