Presentation on theme: "Lecture 13: Sequential Circuits"— Presentation transcript:
1Lecture 13: Sequential Circuits Today’s topics:Carry-lookahead adderClocks and sequential circuitsFinite state machinesReminder: Assignment 5 due on Thursday 10/12,mid-term exam Tuesday 10/24
2Speed of Ripple CarryThe carry propagates thru every 1-bit box: each 1-bit box sequentiallyimplements AND and OR – total delay is the time to go through 64 gates!We’ve already seen that any logic equation can be expressed as thesum of products – so it should be possible to compute the result bygoing through only 2 gates!Caveat: need many parallel gates and each gate may have a verylarge number of inputs – it is difficult to efficiently build such largegates, so we’ll find a compromise:moderate number of gatesmoderate number of inputs to each gatemoderate number of sequential gates traversed
3Computing CarryOut CarryIn1 = b0.CarryIn0 + a0.CarryIn0 + a0.b0 = b1.b0.c0 + b1.a0.c0 + b1.a0.b0 +a1.b0.c0 + a1.a0.c0 + a1.a0.b0 + a1.b1…CarryIn32 = a really large sum of really large productsPotentially fast implementation as the result is computedby going thru just 2 levels of logic – unfortunately, eachgate is enormous and slow
4Generate and Propagate Equation re-phrased:ci+1 = ai.bi + ai.ci + bi.ci= (ai.bi) + (ai + bi).ciStated verbally, the current pair of bits will generate a carryif they are both 1 and the current pair of bits will propagatea carry if either is 1Generate signal = ai.biPropagate signal = ai + biTherefore, ci+1 = gi + pi . ci
5Generate and Propagate c1 = g0 + p0.c0c2 = g1 + p1.c1= g1 + p1.g0 + p1.p0.c0c3 = g2 + p2.g1 + p2.p1.g0 + p2.p1.p0.c0c4 = g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0 + p3.p2.p1.p0.c0Either,a carry was just generated, ora carry was generated in the last step and was propagated, ora carry was generated two steps back and was propagated by boththe next two stages, ora carry was generated N steps back and was propagated by everysingle one of the N next stages
6Divide and ConquerThe equations on the previous slide are still difficult to implement aslogic functions – for the 32nd bit, we must AND every single propagatebit to determine what becomes of c0 (among other things)Hence, the bits are broken into groups (of 4) and each groupcomputes its group-generate and group-propagateFor example, to add 32 numbers, you can partition the task as a tree.
7P and G for 4-bit BlocksCompute P0 and G0 (super-propagate and super-generate) for thefirst group of 4 bits (and similarly for other groups of 4 bits)P0 = p0.p1.p2.p3G0 = g3 + g2.p3 + g1.p2.p3 + g0.p1.p2.p3Carry out of the first group of 4 bits isC1 = G0 + P0.c0C2 = G1 + P1.G0 + P1.P0.c0…By having a tree of sub-computations, each AND, OR gate has fewinputs and logic signals have to travel through a modest set ofgates (equal to the height of the tree)
10Clocks A microprocessor is composed of many different circuits that are operating simultaneously – if each circuit X takes ininputs at time TIX, takes time TEX to execute the logic,and produces outputs at time TOX, imagine thecomplications in co-ordinating the tasks of every circuitA major school of thought (used in most processors builttoday): all circuits on the chip share a clock signal (asquare wave) that tells every circuit when to acceptinputs, how much time they have to execute the logic, andwhen they must produce outputs
11Clock Terminology Rising clock edge Cycle time Falling clock edge 4 GHz = clock speed = =cycle time ps
12Sequential CircuitsUntil now, circuits were combinational – when inputs change, theoutputs change after a while (time = logic delay thru circuit)CombinationalCircuitCombinationalCircuitInputsOutputsWe want the clock to act like a start and stop signal – a “latch” isa storage device that stores its inputs at a rising clock edge andthis storage will not change until the next rising clock edgeClockClockCombinationalCircuitCombinationalCircuitOutputsInputsLatchLatch
13Sequential Circuits Sequential circuit: consists of combinational circuit anda storage elementAt the start of the clockcycle, the rising edgecauses the “state” storageto store some input valuesThis state will not change for an entire cycle (until next rising edge)The combinational circuit has some time to accept the valueof “state” and “inputs” and produce “outputs”Some of the outputs (for example, the value of next “state”) may feedback (but through the latch so they’re only seen in the next cycleInputsStateClockOutputsInputsCombinational Cct
14Designing a Latch An S-R latch: set-reset latch When Set is high, a 1 is storedWhen Reset is high, a 0 is storedWhen both are low, the previous state is preserved (hence,known as a storage or memory element)When both are high, the output is unstable – this set of inputsis therefore not allowedVerify the above behavior!
15D Latch Incorporates a clock The value of the input D signal (data) is stored only when the clockis high – the previous state is preserved when the clock is low
16D Flip Flop Terminology: Latch: outputs can change any time the clock is high (asserted)Flip flop: outputs can change only on a clock edgeTwo D latches in series – ensures that a value is stored only onthe falling edge of the clock
17Sequential CircuitsWe want the clock to act like a start and stop signal – a “latch” isa storage device that stores its inputs at a rising clock edge andthis storage will not change until the next rising clock edgeClockClockCombinationalCircuitCombinationalCircuitOutputsInputsLatchLatch
18Finite State MachineA sequential circuit is described by a variation of a truthtable – a finite state diagram (hence, the circuit is alsocalled a finite state machine)Note that state is updated only on a clock edgeNextstateNext-stateFunctionCurrentStateClockOutputFunctionOutputsInputs
19State DiagramsEach state is shown with a circle, labeled with the statevalue – the contents of the circle are the outputsAn arc represents a transition to a different state, with theinputs indicated on the labelD = 0D = 1This is a state diagram for ___?D = 111D = 0
203-Bit CounterConsider a circuit that stores a number and increments the value onevery clock edge – on reaching the largest value, it starts again from 0Draw the state diagram:How many states?How many inputs?
213-Bit CounterConsider a circuit that stores a number and increments the value onevery clock edge – on reaching the largest value, it starts again from 0Draw the state diagram:How many states?How many inputs?000001010011100101110111000001010011100101110111
22Traffic Light Controller Problem description: A traffic light with only green and red; either theNorth-South road has green or the East-West road has green (bothcan’t be red); there are detectors on the roads to indicate if a car ison the road; the lights are updated every 30 seconds; a light needchange only if a car is waiting on the other roadState Transition Table:How many states?How many inputs?How many outputs?
23State Transition Table Problem description: A traffic light with only green and red; either theNorth-South road has green or the East-West road has green (bothcan’t be red); there are detectors on the roads to indicate if a car ison the road; the lights are updated every 30 seconds; a light mustchange only if a car is waiting on the other roadState Transition Table:CurrState InputEW InputNS NextState=OutputN NN NN EN EE EE NE EE N
24State Diagram State Transition Table: CurrState InputEW InputNS NextState=OutputN NN NN EN EE EE NE EE N