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NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER IPN-CICMICROSE Lab Design of a Multimedia Extension for RISC Processor Eduardo Jonathan Martínez.

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Presentation on theme: "NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER IPN-CICMICROSE Lab Design of a Multimedia Extension for RISC Processor Eduardo Jonathan Martínez."— Presentation transcript:

1 NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER IPN-CICMICROSE Lab Design of a Multimedia Extension for RISC Processor Eduardo Jonathan Martínez Montes Prof. Marco Antonio Ramírez Salinas

2 I.Adder 1.Full adder 2.Ripple carry adder 3.Carry look ahead adder 4.Best adder 5.Adder-Substracter Saturated/Wrapped 8 bits 6.Adder-Substracter Saturated/Wrapped 16 bits II.Multiplier 1.Multiplier 8x8 2.Multiplier 16x16 OUTLINE IPN-CICMICROSE Lab2 III. Vector operations 1.Over view IV.Vector formats 1.OB format 2.OH format V.Prototype 1.Instruction path 2.Prototype 3.Results

3 IPN-CICMICROSE Lab3 ADDERFull adder A full adder is an arithmetic circuit that is used to add three bits. Logic diagramBlock diagram Boolean functions

4 IPN-CICMICROSE Lab4 Ripple Carry Adder (part 1) The carry propagation time is the major speed limiting factor. ADDER

5 IPN-CICMICROSE Lab5 Ripple Carry Adder (part 2)ADDER

6 IPN-CICMICROSE Lab6 Ripple Carry Adder (part 3) Features Resources: 35 LEFmax: MHz Size: 16 bits ADDER

7 IPN-CICMICROSE Lab7 Carry Look Ahead Adder (part 1) It improves speed by reducing the amount of time required to determine carry bits. ADDER

8 IPN-CICMICROSE Lab8 Carry Look Ahead Adder (part 2)ADDER

9 IPN-CICMICROSE Lab9 Carry Look Ahead Adder (part 3) Features Resources: 57 LEFmax: MHz Size: 16 bits ADDER

10 IPN-CICMICROSE Lab10 Kogge Stone Adder (part 1) It is widely considered the fastest adder design possible. ADDER

11 IPN-CICMICROSE Lab11 Kogge Stone Adder (part 2) Black Cell Gray Cell ADDER

12 IPN-CICMICROSE Lab12 Kogge Stone Adder (part 3) Features Resources: 82 LEFmax: MHz Size: 16 bits ADDER

13 IPN-CICMICROSE Lab13 Best adderADDER

14 IPN-CICMICROSE Lab14 Adder-Substracter Saturated/Wrapped 8 bits Features Operations: Adder, SubstracterArithmetic: Saturated, Wrapped Size: 8 bitsUnsigned Integer Resources: 59 LEFmax: MHz ADDER

15 IPN-CICMICROSE Lab15 Adder-Substracter Saturated/Wrapped 16 bits Features Operations: Adder, SubstracterArithmetic: Saturated, Wrapped Size: 16 bitsSigned Integer Resources: 113 LEFmax: MHz ADDER

16 IPN-CICMICROSE Lab16 Multiplier 8x8 Features Operations: MultiplierArithmetic: Saturated, Wrapped Size: 8x8=16 bitsUnsigned Integer Resources: 308 LEFmax: MHz MULTIPLIER

17 IPN-CICMICROSE Lab17 Multiplier 16x16 Features Operations: MultiplierArithmetic: Saturated, Wrapped Size: 16x16=32 bitsSigned Integer Resources: 1,723 LEFmax: MHz MULTIPLIER

18 IPN-CICMICROSE Lab18 VECTOR OPERATIONSOver view Single Instruction Multiple Data, this architecture performs the same operation on multiple data elements in parallel.

19 IPN-CICMICROSE Lab19 Over view (cont.)VECTOR OPERATIONS

20 IPN-CICMICROSE Lab20 OB format  Unsigned.  64 bits vector  8 elements each one 8 bits  Accumulator contains 8 24 bits elements. VECTOR FORMAT

21 IPN-CICMICROSE Lab21 HB format  Signed.  64 bits vector  4 elements each one 16-bits  Accumulator contains 4 48-bits elements. VECTOR FORMAT

22 IPN-CICMICROSE Lab22 Instruction pathPROTOTYPE

23 IPN-CICMICROSE Lab23 Prototype Features Resources: 8,449 LEFmax: MHz ADD, ADDL, ADDASUB, SUBL, SUBA MUL, MULL, MULALDC2, SDC2 No LPM PROTOTYPE

24 IPN-CICMICROSE Lab24 Results ldc2 $v3, 0($0)# $v3 = $s0 let $s0=64'h sdc2 $v3, 0($s0)# $s0 = $v3 ldc2 $v4, 0($0)# $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0)# $s0 = $v3 ldc2 $v5, 0($0)# $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122 sdc2 $v5, 0($s0)# $s0 = $v3 PROTOTYPE

25 IPN-CICMICROSE Lab25 ldc2 $v4, 0($0)# $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0)# $s0 = $v3 ldc2 $v5, 0($0)# $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122 sdc2 $v5, 0($s0)# $s0 = $v3 add.ob $v6,$v4,$v5#$v6 = $v4+$v5 $V4 = 0A 0B 0C 0D 0E 0F AA BB +$V5 = AA BB CC DD EE FF $V6 = B4 C6 D8 EA FC FF BB DD Saturated PROTOTYPEResults (cont.)

26 IPN-CICMICROSE Lab26 ldc2 $v4, 0($0)# $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0)# $s0 = $v3 ldc2 $v5, 0($0)# $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122 sdc2 $v5, 0($s0)# $s0 = $v3 add.ob $v7,$v4,$v5(0)#$v7 = $v4+$v5(0) $V4 = 0A 0B 0C 0D 0E 0F AA BB +$V5(0) = $V7 = 2C 2D 2E 2F CC DD PROTOTYPEResults (cont.)

27 IPN-CICMICROSE Lab27 ldc2 $v4, 0($0)# $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABB sdc2 $v4, 0($s0)# $s0 = $v3 add.ob $v8,$v4,10#$v8 = $v $V4 = 0A 0B 0C 0D 0E 0F AA BB +0A 0A 0A 0A 0A 0A 0A 0A $V8 = B4 C5 PROTOTYPEResults (cont.)

28 IPN-CICMICROSE Lab28 ldc2 $v2, 0($0)# $v3 = $s0 let $s0=64'h sdc2 $v2, 0($s0)# $s0 = $v2 ldc2 $v3, 0($0)# $v3 = $s0 let $s0=64'h sdc2 $v3, 0($s0)# $s0 = $v3 mul.ob $v9,$v2,$v3#$v9 = $v2*$v3 $V2 = X$V3 = $V9 = PROTOTYPEResults (cont.)

29 IPN-CICMICROSE Lab29 Q&A


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