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EELE 367 – Logic Design Module 5 – Sequential Logic Design with VHDL Agenda 1.Flip-Flops & Latches 2.Counters 3.Finite State Machines 4.State Variable Encoding

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Module 5: Sequential Logic Design with VHDL 2 Latches –we’ve learned all of the VHDL syntax necessary to describe sequential storage elements –Let’s review where sequential devices come from SR Latch - To understand the SR Latch, we must remember the truth table for a NOR Gate AB F 00 1 01 0 10 0 11 0

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Module 5: Sequential Logic Design with VHDL 3 Latches SR Latch - when S=0 & R=0, it puts this circuit into a Bi-stable feedback mode where the output is either: Q=0, Qn=1Q=1, Qn=0 AB FAB F 00 1 (U2)00 1 (U1) 01 001 0 (U2) 10 0 (U1)10 0 11 011 0 0 0 0 0 1 11 1 0 0 0 0

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Module 5: Sequential Logic Design with VHDL 4 Latches SR Latch - we can force a known state using S & R: Set (S=1, R=0)Reset (S=0, R=1) AB FAB F 00 1 (U1)00 1 (U2) 01 001 0 (U1) 10 0 (U2)10 0 11 0 (U2)11 0 (U1) 1 1 0 1 0 00 0 1 0 1 1

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Module 5: Sequential Logic Design with VHDL 5 Latches SR Latch - we can write a Truth Table for an SR Latch as follows S RQ Qn. 0 0Last QLast Qn - Hold 0 10 1 - Reset 1 01 0 - Set 1 10 0 - Don’t Use - S=1 & R=1 forces a 0 on both outputs. However, when the latch comes out of this state it is metastable. This means the final state is unknown.

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Module 5: Sequential Logic Design with VHDL 6 Latches S’R’ Latch - we can also use NAND gates to form an inverted SR Latch S’ R’Q Qn. 0 01 1- Don’t Use 0 11 0 - Set 1 00 1 - Reset 1 1 Last Q Last Qn - Hold

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Module 5: Sequential Logic Design with VHDL 7 Latches SR Latch w/ Enable - we then can add an enable line using NAND gates - remember the Truth Table for a NAND gate AB F 00 1 - a 0 on any input forces a 1 on the output 01 1 - when C=0, the two EN NAND Gate outputs are 1, which forces “Last Q/Qn” 10 1 - when C=1, S & R are passed through INVERTED 11 0

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Module 5: Sequential Logic Design with VHDL 8 Latches SR Latch w/ Enable - the truth table then becomes C S RQ Qn. 1 0 0Last Q Last Qn - Hold 1 0 10 1 - Reset 1 1 01 0 - Set 1 1 1 1 1 - Don’t Use 0 x x Last Q Last Qn - Hold

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Module 5: Sequential Logic Design with VHDL 9 Latches D Latch - a modification to the SR Latch where R = S’ creates a D-latch - when C=1, Q <= D - when C=0, Q <= Last Value C DQ Qn. 1 00 1- track 1 11 0 - track 0 xLast Q Last Qn - Hold

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Module 5: Sequential Logic Design with VHDL 10 Latches VHDL of a D Latch architecture Dlatch_arch of Dlatch is begin LATCH : process (D,C) begin if (C=‘1’) then Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture;

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Module 5: Sequential Logic Design with VHDL 11 Flip Flops D-Flip-Flops - we can combine D-latches to get an edge triggered storage device (or flop) - the first D-latch is called the “Master”, the second D-latch the “Slave” Master Slave CLK=0, Q<=D “Open”CLK=0, Q<=Q “Close” CLK=1, Q<=Q “Closed”CLK=1, Q<=D “Open” - on a rising edge of clock, D is “latched” and held on Q until the next rising edge

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Module 5: Sequential Logic Design with VHDL 12 Flip Flops VHDL of a D-Flip-Flop architecture DFF_arch of DFF is begin FLOP : process (CLK) begin if (CLK’event and CLK=1) then -- recognized by all synthesizers as DFF Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture;

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Module 5: Sequential Logic Design with VHDL 13 Counters Counters - special name of any clocked sequential circuit whose state diagram is a circle - there are many types of counters, each suited for particular applications

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Module 5: Sequential Logic Design with VHDL 14 Counters Binary Counter - state machine that produces a straight binary count - for n-flip-flops, 2 n counts can be produced - the Next State Logic "F" is a combinational SOP/POS circuit - the speed will be limited by the Setup/Hold and Combinational Delay of "F" - this gives the maximum number of counts for n-flip flops

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Module 5: Sequential Logic Design with VHDL 15 Counters Toggle Flop - a D-Flip-Flop can product a "Divide-by-2" effect by feeding back Qn to D - this topology is also called a "Toggle Flop"

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Module 5: Sequential Logic Design with VHDL 16 Counters Ripple Counter - Cascaded Toggle Flops can be used to form rippled counter - there is no Next State Logic - this is slower than a straight binary counter due to waiting for the "ripple" - this is good for low power, low speed applications

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Module 5: Sequential Logic Design with VHDL 17 Counters Synchronous Counter with ENABLE - an enable can be included in a "Synchronous" binary counter using Toggle Flops - the enabled is implemented by AND'ing the Q output prior to the next toggle flop - this gives us the "ripple" effect, but also gives the ability to run synchronously - a little faster, but still less gates than a straight binary circuit

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Module 5: Sequential Logic Design with VHDL 18 Counters Shift Register - a chain of D-Flip-Flops that pass data to one another - this is good for "pipelining" - also good for Serial-to-Parallel conversion - for n-flip-flops, the data is present at the final state after n clocks

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Module 5: Sequential Logic Design with VHDL 19 Counters Ring Counter - feeding the output of a shift register back to the input creates a "ring counter" - also called a "One Hot" - The first flip-flop needs to reset to 1, while the others reset to 0 - for n flip-flops, there will be n counts

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Module 5: Sequential Logic Design with VHDL 20 Counters Johnson Counter - feeding the inverted output of a shift register back to the input creates a "Johnson Counter" - this gives more states with the same reduced gate count - all flip-flops can reset to 0 - for n flip-flops, there will be 2n counts

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Module 5: Sequential Logic Design with VHDL 21 Counters Linear Feedback Shift Register (LFSR) Counter - all of the counters based off of shift registers give far less states than the 2 n counts that are possible - a LFSR counter is based off of the theory of finite fields - created by French Mathematician Evariste Galois (1811-1832) - for each size of shift register, a feedback equation is given which is the sum modulo 2 of a certain set of output bits - this equation produces the input to the shift register - this type of counter can produce 2 n -1 counts, nearly the maximum possible

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Module 5: Sequential Logic Design with VHDL 22 Counters Linear Feedback Shift Register (LFSR) Counter - the feedback equations are listed in Table 8.26 of the textbook - It is defined that bits always shift from X n-1 to X 0 (or Q 0 to Q n-1 ) as we defined the shift register previously - they each use XOR gates (sum modulo 2) of particular bits in the register chain ex) nFeedback Equation 2X2 = X1 X0 3X3 = X1 X0 4X4 = X1 X0 5X5 = X2 X0 6X6 = X1 X0 7X7 = X3 X0 8X8 = X4 X3 X2 X0 : : : :

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Module 5: Sequential Logic Design with VHDL 23 Counters Linear Feedback Shift Register (LFSR) Counter ex) 4-flip-flop LFSR Counter Feedback Equation = X1 X0 (or Q2 Q3 as we defined it) #Q(0:3) Sin 0 1000 0 1 0100 0 2 0010 1 3 1001 1 4 1100 0 5 0110 1 6 1011 0 7 0101 1 8 1010 1 9 1101 1 10 1110 1 11 1111 0 12 0111 0 13 0011 0 14 0001 1- this is 2 n -1 unique counts repeat 1000

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Module 5: Sequential Logic Design with VHDL 24 Counters Counters in VHDL - strong type casting in VHDL can make modeling counters difficult (at first glance) - the reason for this is that the STANDARD and STD_LOGIC Packages do not define "+", "-", or inequality operators for BIT_VECTOR or STD_LOGIC_VECTOR types

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Module 5: Sequential Logic Design with VHDL 25 Counters Counters in VHDL - there are a couple ways that we get around this 1) Use the STD_LOGIC_UNSIGNED Package - this package defines "+" and "-" functions for STD_LOGIC_VECTOR - we can use +1 just like normal - the vector will wrap as suspected (1111 - 0000) - one catch is that we can't assign to a Port - we need to create an internal signal of STD_LOGIC_VECTOR for counting - we then assign to the Port at the end

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Module 5: Sequential Logic Design with VHDL 26 Counters Counters in VHDL using STD_LOGIC_UNSIGNED use IEEE.STD_LOGIC_UNSIGNED.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

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Module 5: Sequential Logic Design with VHDL 27 Counters Counters in VHDL using STD_LOGIC_UNSIGNED architecture counter_arch of counter is signal count_temp : std_logic_vector(3 downto 0);-- Notice internal signal begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= "0000"; elsif (Clock='1' and Clock'event) then if (Direction='0') then count_temp <= count_temp + '1'; -- count_temp can be used on both LHS and RHS else count_temp <= count_temp - '1'; end if; end process; Count_Out <= count_temp; -- assign to Port after the process end counter_arch;

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Module 5: Sequential Logic Design with VHDL 28 Counters Counters in VHDL 2) Use integers for the counter and then convert back to STD_LOGIC_VECTOR - STD_LOGIC_ARITH is a Package that defines a conversion function - the function is: conv_std_logic_vector (ARG, SIZE) - functions are defined for ARG = integer, unsigned, signed, STD_ULOGIC - SIZE is the number of bits in the vector to convert to, given as an integer - we need to keep track of the RANGE and Counter Overflow

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Module 5: Sequential Logic Design with VHDL 29 Counters Counters in VHDL using STD_LOGIC_ARITH use IEEE.STD_LOGIC_ARITH.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

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Module 5: Sequential Logic Design with VHDL 30 Counters Counters in VHDL using STD_LOGIC_ARITH architecture counter_arch of counter is signal count_temp : integer range 0 to 15;-- Notice internal integer specified with Range begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= 0; -- integer assignment doesn't requires quotes elsif (Clock='1' and Clock'event) then if (count_temp = 15) then count_temp <= 0; -- we manually check for overflow else count_temp <= count_temp + 1; end if; end process; Count_Out <= conv_std_logic_vector (count_temp, 4);-- convert integer into a 4-bit STD_LOGIC_VECTOR end counter_arch;

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Module 5: Sequential Logic Design with VHDL 31 Counters Counters in VHDL 3) Use UNSIGNED data types #'s - STD_LOGIC_ARITH also defines "+", "-", and equality for UNSIGNED types - UNSIGNED is a Data type defined in STD_LOGIC_ARITH - UNSIGNED is an array of STD_LOGIC - An UNSIGNED type is the equivalent to a STD_LOGIC_VECTOR type - the equality operators assume it is unsigned (as opposed to 2's comp SIGNED) Pro's and Cons - using integers allows a higher level of abstraction and more functionality can be included - easier to write unsynthesizable code or code that produces unwanted logic - both are synthesizable when written correctly

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Module 5: Sequential Logic Design with VHDL 32 Counters Ring Counters in VHDL - to mimic the shift register behavior, we need access to the signal value before and after clock'event - consider the following concurrent signal assignments: architecture …. begin Q0 <= Q3; Q1 <= Q0; Q2 <= Q1; Q3 <= Q2; end architecture… - since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire

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Module 5: Sequential Logic Design with VHDL 33 Counters Ring Counters in VHDL - since a process doesn't assign the signal values until it suspends, we can use this to model the "before and after" behavior of a clock event. process (Clock, Reset) begin if (Reset = '0') then Q0<='1'; Q1<='0';Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=Q3;Q1<=Q0;Q2<=Q1;Q3<=Q2; end if; end process - notice that the signals DO NOT appear in the sensitivity list. If they did the process would continually execute and not be synthesized as a flip-flop structure

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Module 5: Sequential Logic Design with VHDL 34 Counters Johnson Counters in VHDL process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0';Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=not Q3;Q1<=Q0;Q2<=Q1;Q3<=Q2; end if; end process

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Module 5: Sequential Logic Design with VHDL 35 Counters Linear Feedback Shift Register Counters in VHDL process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0';Q2<='0'; Q3<='0'; elsif (Clock'event and Clock='1') then Q0<=Q3 xor Q2;Q1<=Q0;Q2<=Q1;Q3<=Q2; end if; end process

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Module 5: Sequential Logic Design with VHDL 36 Counters Multiple Processes - we can now use State Machines to control the start/stop/load/reset of counters - each are independent processes that interact with each other through signals - a common task for a state machine is: 1) at a certain state, load and enable a counter 2) go to a state and wait until the counter reaches a certain value 3) when it reaches the certain value, disable the counter and continue to the next state - since the counter runs off of a clock, we know how long it will count between the start and stop

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Module 5: Sequential Logic Design with VHDL 37 State Machines State Machines - there is a basic structure for a Clocked, Synchronous State Machine 1) State Memory(i.e., flip-flops) 2) Next State Logic “G”(combinational logic) 3) Output Logic “F”(combinational logic) we’ll revisit F later… - if we keep this structure in mind while designing digital machines in VHDL, then it is a very straight forward task - Each of the parts of the State Machine are modeled with individual processes - let’s start by reviewing the design of a state machine using a manual method

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Module 5: Sequential Logic Design with VHDL 38 State Machines State Machines “Mealy Outputs” – outputs depend on the Current_State and the Inputs

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Module 5: Sequential Logic Design with VHDL 39 State Machines State Machines “Moore Outputs” – outputs depend on the Current_State only

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Module 5: Sequential Logic Design with VHDL 40 State Machines State Machines - the steps in a state machine design are: 1) Word Description of the Problem 2) State Diagram 3) State/Output Table 4) State Variable Assignment 5) Choose Flip-Flop type 6) Construct F 7) Construct G 8) Logic Diagram

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Module 5: Sequential Logic Design with VHDL 41 State Machines State Machine Example “Sequence Detector” 1) Design a machine by hand that takes in a serial bit stream and looks for the pattern “1011”. When the pattern is found, a signal called “Found” is asserted 2) State Diagram

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Module 5: Sequential Logic Design with VHDL 42 State Machines State Machine Example “Sequence Detector” 3) State/Output Table Current_StateInNext_StateOut (Found) S00S00 1S10 S10S20 1S00 S20S00 1S30 S30S00 1S01

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Module 5: Sequential Logic Design with VHDL 43 State Machines State Machine Example “Sequence Detector” 4) State Variable Assignment – let’s use binary Current_StateInNext_StateOut Q1 Q0 Q1* Q0* Found 0 00 0 00 1 0 10 0 10 1 00 1 0 00 1 00 0 00 1 1 10 1 10 0 00 1 0 01 5) Choose Flip-Flop Type - 99% of the time we use D-Flip-Flops

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Module 5: Sequential Logic Design with VHDL 44 State Machines State Machine Example “Sequence Detector” 6) Construct Next State Logic “F” Q1* = Q1’∙Q0∙In’ + Q1∙Q0’∙In Q0* = Q0’∙In 01 00 Q1 Q0 In 0001 0 1 0 1 2 3 In Q1 0 0 6 7 0 1 4 5 1110 Q0 00 10 Q1 Q0 In 0001 0 1 0 1 2 3 In Q1 0 0 6 7 0 1 4 5 1110 Q0

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Module 5: Sequential Logic Design with VHDL 45 State Machines State Machine Example “Sequence Detector” 7) Construct Output Logic “G” Found = Q1∙Q0∙In 8) Logic Diagram - for large designs, this becomes impractical 00 00 Q1 Q0 In 0001 0 1 0 1 2 3 In Q1 0 1 6 7 0 0 4 5 1110 Q0

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Module 5: Sequential Logic Design with VHDL 46 State Machines in VHDL State Memory - we use a process that updates the “Current_State” with the “Next_State” - we describe DFF’s using (CLK’event and CLK=‘1’) - this will make the assignment on the rising edge of CLK STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') then Current_State <= Next_State; end if; end process; - at this point, we need to discuss State Names

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Module 5: Sequential Logic Design with VHDL 47 State Machines in VHDL State Memory using “User-Enumerated Data Types" - we always want to use descriptive names for our states - we can use a user-enumerated type for this type State_Type is (S0, S1, S2, S3); signal Current_State : State_Type; signal Next_State : State_Type; - this makes our simulations very readable. State Memory using “Pre-Defined Data Types" - we haven’t encoded the variables though, we can either leave it to the synthesizer or manually do it subtype State_Type is BIT_VECTOR (1 downto 0); constant S0 : State_Type := “00”; constant S1 : State_Type := “01”; constant S2 : State_Type := “10”; constant S3 : State_Type := “11”; signal Current_State : State_Type; signal Next_State : State_Type;

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Module 5: Sequential Logic Design with VHDL 48 State Machines in VHDL State Memory with “Synchronous RESET” STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') then if (Reset = ‘1’) then Current_State <= S0;-- name of “reset” state to go to else Current_State <= Next_State; end if; end if; end process; - this design will only observe RESET on the positive edge of clock (i.e., synchronous)

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Module 5: Sequential Logic Design with VHDL 49 State Machines in VHDL State Memory with “Asynchronous RESET” STATE_MEMORY : process (CLK, Reset) begin if (Reset = ‘1’) then Current_State <= S0;-- name of “reset” state to go to elsif (CLK’event and CLK='1') then Current_State <= Next_State; end if; end process; - this design is sensitive to both RESET and the positive edge of clock (i.e., asynchronous)

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Module 5: Sequential Logic Design with VHDL 50 State Machines in VHDL Next State Logic “F” - we use another process to construct “F”

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Module 5: Sequential Logic Design with VHDL 51 State Machines in VHDL Next State Logic “F” - the process will be combinational logic NEXT_STATE_LOGIC : process (In, Current_State) begin case (Current_State) is when S0 => if (In=‘0’) then Next_State if (In=‘0’) then Next_State if (In=‘0’) then Next_State if (In=‘0’) then Next_State <= S0; elsif(In=‘1’) then Next_State <= S0; end if; end case; end process;

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Module 5: Sequential Logic Design with VHDL 52 State Machines in VHDL Output Logic “G” - we use another process to construct “G” - the expressions in the sensitivity list dictate Mealy/Moore type outputs - for now, let’s use combinational logic for G (we’ll go sequential later)

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Module 5: Sequential Logic Design with VHDL 53 State Machines in VHDL Output Logic “G” - Mealy type outputs OUTPUT_LOGIC : process (In, Current_State) begin case (Current_State) is when S0 => if (In=‘0’) then Found if (In=‘0’) then Found if (In=‘0’) then Found if (In=‘0’) then Found <= 0; elsif(In=‘1’) then Found <= 1; end if; end case; end process;

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Module 5: Sequential Logic Design with VHDL 54 State Machines in VHDL Output Logic “G” - Moore type outputs OUTPUT_LOGIC : process (Current_State) begin case (Current_State) is when S0 => Found Found Found Found <= 1; end case; end process; - this is just an example, it doesn’t really work for this machine

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Module 5: Sequential Logic Design with VHDL 55 State Machines in VHDL Example - Let’s design a 2-bit Up/Down Gray Code Counter using User-Enumerated State Encoding - In=0, Count Up - In=1, Count Down - this will be a Moore Type Machine - no Reset

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Module 5: Sequential Logic Design with VHDL 56 State Machines in VHDL Example - let’s collect our thoughts using a State/Output Table Current_StateInNext_StateOut CNT00CNT100 1CNT3 CNT10CNT201 1CNT0 CNT20CNT311 1CNT1 CNT30CNT010 1CNT2

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Module 5: Sequential Logic Design with VHDL 57 State Machines in VHDL Example architecture CNT_arch of CNT is type State_Type is (CNT0, CNT1, CNT2, CNT3); signal Current_State, Next_State : State_Type; begin STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') then Current_State if (In=‘0’) then Next_State if (In=‘0’) then Next_State if (In=‘0’) then Next_State if (In=‘0’) then Next_State <= CNT0; elsif(In=‘1’) then Next_State <= CNT2; end if; end case; end process; OUTPUT_LOGIC : process (Current_State) begin case (Current_State) is when CNT0 => Out Out Out Out <= “10”; end case; end process; end architecture;

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Module 5: Sequential Logic Design with VHDL 58 State Machines in VHDL Example - in the lab, we may want to observe the states on the LEDs - in this case we want to explicitly encode the STATE variables architecture CNT_arch of CNT is subtype State_Type is BIT_VECTOR (1 dowto 0); constant CNT0 : State_Type := “00”; constant CNT1 : State_Type := “01”; constant CNT2 : State_Type := “10”; constant CNT3 : State_Type := “11”; signal Current_State, Next_State : State_Type;

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Module 5: Sequential Logic Design with VHDL 59 State Encoding State Variable Encoding - we can decide how we encode our state variables - there are advantages/disadvantages to different techniques Binary Encoding - straight encoding of states S0 = “00” S1 = “01” S2 = “10” S3 = “11” - for n states, there are log(n)/log(2) flip-flops needed - this gives the Least # of Flip-Flops - Good for “Area” constrained designs - Drawbacks:- multiple bits switch at the same time = Increased Noise & Power - the Next State Logic “F” is multi-level = Increased Power and Reduced Speed

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Module 5: Sequential Logic Design with VHDL 60 State Encoding Gray-Code Encoding - encoding using a gray code where only one bits switches at a time S0 = “00” S1 = “01” S2 = “11” S3 = “10” - for n states, there are log(n)/log(2) flip-flops needed - this gives low Power and Noise due to only one bit switching - Good for “Power/Noise” constrained designs - Drawbacks:- the Next State Logic “F” is multi-level = Increased Power and Reduced Speed

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Module 5: Sequential Logic Design with VHDL 61 State Encoding One-Hot Encoding - encoding one flip-flop for each state S0 = “0001” S1 = “0010” S2 = “0100” S3 = “1000” - for n states, there are n flip-flops needed - the combination logic for F is one level (i.e., a Decoder) - Good for Speed - Especially good for FPGA due to “Programmable Logic Block” - Drawbacks:- takes more area

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Module 5: Sequential Logic Design with VHDL 62 State Encoding State Encoding Trade-Offs - We typically trade off Speed, Area, and Power speed power area One-Hot BinaryGray

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Module 5: Sequential Logic Design with VHDL 63 Pipelined Outputs Pipelined Outputs - Having combinational logic drive outputs can lead to: - multiple delay paths through the logic - potential for glitches - Both reduce the speed at which the system clock can be ran - A good design practice is to pipeline the outputs (i.e., use DFF’s as the output driver)

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Module 5: Sequential Logic Design with VHDL 64 Pipelined Outputs Pipelined Outputs - This gives a smaller Data Uncertainty window on the output - The only consideration is that the output is not present until one clock cycle later

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Module 5: Sequential Logic Design with VHDL 65 Pipelined Outputs Pipelined Outputs - we use a 4 th process for this stage of the State Machine PIPELINED_OUTPUTS : process (CLK) begin if (CLK’event and CLK='1') then Out <= Next_Out; end if; end process;

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Module 5: Sequential Logic Design with VHDL 66 Asynchronous Inputs Asynchronous Inputs - Real world inputs are not phase-locked to the clock - this means an input can change within the Setup/Hold window of the clock - this can send the Machine into an incorrect state - we always want to “synchronize” inputs so that this doesn’t happen

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Module 5: Sequential Logic Design with VHDL 67 Asynchronous Inputs Asynchronous Inputs - We use D-Flip-Flops to take in the input - with one D-Flip-Flop, the input can still occur within the Setup/Hold window - the output of the first DFF may be metastable for a moment of time (trecovery) - a second DFF is used to latch in the metastable input after it has had time to settle - the output of the second flip-flop is now stable and synchronized as long as: T clk > t recovery + t comb + t setup - where t comb is the delay of any combinational logic in the input path

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