Presentation is loading. Please wait.

Presentation is loading. Please wait.

Interconnect Intermittency Detection with

Similar presentations

Presentation on theme: "Interconnect Intermittency Detection with"— Presentation transcript:

1 Interconnect Intermittency Detection with

2 Agenda What is SJ BIST? Interconnect Reliability – Background
SJ BIST Basics SJ BIST Operation SJ BIST Application Summary & Conclusions

3 What is SJ BIST? SJ BIST = Solder Joint Built-in Self-Test
Original solution enabling the verification and validation of solder joint interconnect reliability Originally developed for FPGA-BGA applications Can be applied to validate the integrity and reliability of any type of interconnection

4 BGA – PCB Relationship: Die, package, wiring, pins

5 Defects: Location of Cracks/Fractures
Corner pins likely to fail first High stress areas, and corners of the BGA package and die

6 Solder Balls, Cracks and Fractures

7 Mechanisms of Failure Fatigue fractures (cracks) are caused by thermo-mechanical stress/strain During periods of high stress, fractured bumps tend to momentarily open and cause intermittent faults of high resistance for periods of ns to µs Over time, contamination and oxidation films occur on the fractured faces: the effective contact area becomes smaller and smaller Transient opens can be detected by event detectors Oxide-covered area

8 Mechanics of Failure HALT results - Pulled FPGA – Damaged Solder Balls
Undamaged Damaged: Cracked Cracked, not detectable Fractured, detectable

9 Fractures and Intermittency

10 Defects: Fractures & Intermittency

11 Intermittent Faults Faults are intermittent: confirmed by CAVE, Auburn Univ., German automobile manufacturer, BAE Systems and other firms Occur during periods of increasing strain Multiple occurrences per cycle Industry standard: 200 ohms +, 200 ns +

12 Intermittencies With present technology, reported electronic system problems in the field cannot be duplicated at the service point or in the lab “Three/Four-letter” words (CND, NTF, RTOK) Could Not Duplicate (CND) No Trouble Found (NTF) Retest OK (RTOK) 50 to 80% of these CND/NTF/RTOK problem categories are reported by service personnel. Major culprits – Solder joint intermittencies and NBTI effects in deep submicron ICs

13 SJ BIST Objectives & Features
Detection of impending interconnect failures Unique in-situ testing in operating circuits Technology-independent Feature and Benefits Detects ball fractures prior to catastrophic failure of circuit Provides actionable maintenance data Independently tested and verified Endorsed by leading automotive and aerospace customers

14 SJ BIST Implementation
SJ BIST Control Functional I/O SJ BIST I/O Functional Circuitry SJ BIST SJ BIST interacts with the host circuit SJ BIST runs concurrently with host circuit SJ BIST requires dedicated I/0

15 SJ BIST Implementation
SJ BIST Control Functional I/O SJ BIST I/O Functional Circuitry SJ BIST SJ BIST receives its control signals (clock, enable) from the host and sends its output to the outside world SJ BIST runs concurrently with host circuit SJ BIST requires dedicated I/0

16 SJ BIST Implementation
SJ BIST Control Functional I/O SJ BIST I/O Functional Circuitry SJ BIST SJ BIST is on the same silicon as its host circuit but is interacting directly with the outside world SJ BIST runs concurrently with host circuit SJ BIST requires dedicated I/0

17 SJ BIST™ Operation Similar to a simple memory test: W0 – R0; W1 – R1
Runs concurrently with host circuit Verilog/VHDL core (patent pending) Each core tests two I/O pins Pins are externally wired together Small capacitor connected to the two pins

18 SJ BIST Operation Healthy Solder Joint Writes a “1” and reads a “1”

19 SJ BIST Operation Faulty Solder Joint Writes a “1” but reads a “0”

20 SJ BIST Capacitor Function of operating frequency & desired sensitivity 300 Ohm 100 Ohm 10 Ohm

21 SJ BIST Application Requirement:
Interconnect path SJ BIST On-chip interconnects Die to substrate (incl. bumps) Requirement: Interconnect path dedicated for SJ BIST Die to board (incl. bumps & balls)

22 SJ BIST Application Testing On-chip Interconnect
Need for dedicated on-chip path between SJ BIST™ Observation pins

23 SJ BIST Application Testing Die to Substrate

24 SJ BIST Application Testing Die to Board

25 SJ BIST Simulation Results
LVTTL − Low Voltage TTL Output Low ≤0.4V High ≥2.4V Input Low ≤0.8V High ≥2.0V LVTTL stands for Low Voltage TTL (referring to low voltage TTL levels of components with TTL compliant I/O circuitry). The simulation results that were once obtained and that are shown in the next slide) were done accordingly. The purpose of this slide is to show the LVTTL I/O levels as to provide the base for interpretation of the simulation results that follow.

26 SJ BIST Simulation Results
Clock = 50 MHz Charge pulse t=20 ns C1=57 pF (47 pF capacitor)+(10 pF of the I/O port and wires) The time constant =R1·C1 and t determine the charge voltage In the prohibited zone (0.8 to 2.0 V) there is guaranteed detection Capacitor charging R1=175Ω R1=700Ω

27 SJ BIST Simulation Results
Voltage across the test capacitor One bump is connected with a 700 Ω resistor. So the time constant =R1·C1 increases and the test capacitor is charged with only 0.8 V. A logical ‘0‘ instead of a ‘1‘ is read, a fault is detected. 700 Ω Fault: Same as electrical model and PSPICE simulation

28 SJ BIST Application Results
SJ BIST specifications Sensitivity: as least as low as 100 Ω Resolution: guaranteed two clock periods Detectable intermittency: as short as ½ of a clock period 50 MHz clock 40-ns guaranteed detection 10-ns detection possible 100 Ω fault 1 MHz clock

29 SJ BIST Application Results
Independent test results by German automotive firm Confirmed the same results as obtained by Ridgetop Group No false alarms

30 SJ BIST I/O Input (Control) Test Pins Output (to host)
Clock, Enable & Reset Test Pins 2 bidirectional I/O pins: TP0 & TP1 Output (to host) Failure Flags (fault was detected on TP0/TP1) Active fault flags (fault is active on TP0/TP1 at the moment of interrogation of SJ BIST) Failure counts (2 8-bit values related to number of faults detected on TP0 and TP1 respectively)

31 Requires dedicated I/O + capacitor Runs concurrently
SJ BIST Summary Available as: Verilog/VHDL core Microcontroller code Requires dedicated I/O + capacitor Runs concurrently Interconnect reliability verification Process qualification Lifetime observation

32 SJ BIST HALT for Process Qualification

33 Contact Information Ridgetop Group, Inc. Hans Manhaeve Office: 3580 West Ina Rd. Tucson, AZ

34 Ridgetop Products and Services

35 Ridgetop SPI Products & Services
nanoDFM Verification Monitors PDKChek™ - Die-Level Process Monitors Mismatch: ∆VT,∆I(on), ∆R, ∆C, YieldMaxx™ - Die-Level Variation Visualization Sentinel Silicon Prognostic Cores NBTI TDDB Hot Carrier Radiation Exposure ProChek Semiconductor Process Characterization System - NBTI - PBTI - TDDB - Hot Carrier Radiation - Stress Migration - VT Degradation - Electromigration Q-Star Test™ Current Monitors IDDQ IDDT ISSQ On-chip & On-board Single- & multi-site InstaCell™ Mixed Signal Cores ADC – Analog to Digital Converters DAC – Digital to Analog Converters Op Amps, References ,and Comparators InstaBIST™ Test Cells SJ-BIST BGA Solder Joint Built-in Test ADC-BIST Self-testing Data Converters TopAct® Radiation Transport Analysis Acceleration Design Services ASICs Cores Radiation-hardening MEMS Custom instruments

36 Advantages of PDKChek PDKChek Scribe Line Transistors DLPM
Uses test structure on the host die Requires additional test fixture Testing can occur pre- and post-packaging Lost when wafers are sliced Performs quick production test Delicate probe measurement: inaccurate and time-consuming Measures parameters that are useful to the designer May not directly measure important parameters; needs additional characterization Data is application-specific DUTs are extracted from the host design PDK models may not provide accurate predictions DLPM Scribe Line Transistor 36

37 Example: Product Yield Analysis of 90nm Process
PDKChek embedded in the ADC Example of GDSII Layout for the Ridgetop 14-bit Pipeline ADC 37

38 Chip-Level Prognostic Solutions and Applications
Prognostic Cell Library Some Target Applications NBTI Cell Flash memory, SRAM HCI Cell ADCs, biasing circuits, analog, and slow-speed switching circuits TDDB Cell Flash memory Metal Migration Cell Damascene process stress, high current density application Products described herein are covered by U.S. patents: 7,239, ,196, ,271,608. Other patents are pending.

39 What is ProChek? ProChek is an innovative low-cost technique to very rapidly characterize the intrinsic reliability of deep submicron nanotechnology CMOS processes (bulk CMOS, SOI and SiGe) 1 min

40 Characteristics of ProChek
Targets bulk CMOS, SOI, SiGe reliability concerns NBTI / PBTI, TDDB, HC, EM, SM, TID Test Coupon As little as 1 * 1 mm chip area MPW for lower cost 32 – 1024 devices can be tested in parallel for maximum throughput On-chip per transistor heaters to 325 °C, greatly reducing test time Synthesizable (except for on-chip heaters) to speed deployment Benchtop Tester Fully programmable test conditions cover DC and AC stress cases Portable and compact ATE not needed Host Controller Easy-to-use software GUI Rich suite of built-in reliability test templates Data processing capabilities 2 min

41 InstaCell™ IP Core Library
The cores provided by Ridgetop are "Silicon Proven" and have documented reports available. Ridgetop has designed cores for use in the IBM, TSMC, and AMI processes. Analog-to-Digital Converter (ADC) Cores Digital-to-Analog Converter (DAC) Cores Bandgap Reference (BGR) Core Op-amp Core

42 Design Services Ridgetop maintains a complete Cadence design flow, and has designed circuitry down to the 45 nm process node. Ridgetop also has a line of predesigned and characterized IP blocks that can be used to accelerate the time-to-market for your systems. Examples include precision bandgap references, op-amps, comparators, ADCs, DACs and test structures. Our design services include: Analog/mixed-signal and gate array integrated circuits with varying process nodes of 0.5 μm down to 45 nm High-speed, high performance, high linearity ADC and DAC design Fuel Cell and Battery Management System components FPGA-based designs, from basic specification to gate level, with timing analysis and programming IP blocks of specialized functionality Modeling and simulation Completion of back-end design from existing EDIF/SPICE to GDSII layout Rescaling “legacy” designs to smaller process geometries Radiation-hardened/foundry-specific designs

43 Q-Star Test IDDQ ,IDDT, ISSQ and other precision current measurement instruments for characterization and test On-board modules and on-chip sensors Test and DFT consulting and training services 70 semiconductor companies and 700 instruments installed Developed by Ridgetop Europe

44 Q-Star Test Measurement Solutions
Static (Quiescent) Current Measurement Instruments (IDDQ/ISSQ) Standard and advanced IDDQ tests Stand-by current measurements Power-down current measurements Bias current measurements Average current measurements Analog DC and low frequency current measurements …. Dynamic Current Measurement Instruments (IDDT) Dynamic and transient (IDDT) current tests Power profiling of circuits and systems Active current consumption E-fuse programming validation (c) Q-Star Test, Confidential

45 Why Ridgetop? Ridgetop Group Delivers
(All project contributors PhD or advanced degree) World Class Engineering Staff World Leaders in Electronic Prognostics (Awarded most gov’t contracts) (Expansive portfolio of electronic prognostic solutions) Domain Expertise IP Easily Configured to Target Applications (Seamless integration and porting) (Dedicated service and support personnel for on demand assistance) Customer Service (Strive to improve/upgrade existing IP) Commitment to Innovation

46 For more information about Ridgetop’s products and capabilities please visit:

Download ppt "Interconnect Intermittency Detection with"

Similar presentations

Ads by Google