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ILP: Software Approaches Bazat pe slide-urile lui Vincent H. Berk.

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Presentation on theme: "ILP: Software Approaches Bazat pe slide-urile lui Vincent H. Berk."— Presentation transcript:

1 ILP: Software Approaches Bazat pe slide-urile lui Vincent H. Berk

2 2/12 HW Support for More ILP  Avoid branch prediction by turning branches into conditionally executed instructions:  If (X) then A = B op C else NOP If false, then neither store result nor cause exception Expanded ISA of Alpha, MIPS, PowerPC, SPARC have conditional move; PA-RISC can annul any following instruction. IA-64: 61 1-bit condition fields selected so conditional execution of any instruction  Drawbacks to conditional instructions Still takes a clock even if “annulled” Stall if condition evaluated late Complex conditions reduce effectiveness; condition becomes known late in pipeline X A = B op C

3 3/12 Software Pipelining  Observation: if iterations from loops are independent, then can get more ILP by taking instructions from different iterations  Software pipelining: reorganizes loops so that each iteration is made from instructions chosen from different iterations of the original loop Iteration 0 1 2 3 4 pipelined

4 4/12 4 SW Pipelining Example 1LDF0, 0 (R1)LDF0, 0 (R1) 2ADDDF4, F0, F2ADDDF4, F0, F2 3SD0 (R1), F4LDF0, –8 (R1) 4LDF6, –8 (R1)1SD0 (R1), F4Stores M[i] 5ADDDF8, F6, F22ADDDF4, F0, F2Adds to M[i-1] 6SD–8, (R1), F83LDF0, –16 (R1)Loads M[i-2] 7LDF10, –16 (R1)4SUBIR1, R1, #8 8ADDDF12, F10, F25BNEZR1, LOOP 9SD–16 (R1), F12SD0 (R1), F4 10SUBIR1, R1, #24ADDDF4, F0, F2 11BNEZR1, LOOPSD–8 (R1), F4 Read F4 Read F0 SDIFIDEXMemWB Write F4 ADDIFIDEXMemWB LDIFIDEXMemWB Write F0 Before: Unrolled 3 timesAfter: Software Pipelined

5 5/12 5 SW Pipelining Example  Symbolic Loop Unrolling Smaller code space Overhead paid only once vs. each iteration in loop unrolling 100 iterations = 25 loops with 4 unrolled iterations each Number of overlapped operations Software Pipelining (a) Software pipeliningTime Loop Unrolling (b) Loop unrolling Time Number of overlapped operations

6 6/12 Trace Scheduling  Focus on critical path (trace selection) Compiler has to decide what the critical path (the trace) is Most likely basic blocks are put in the trace Loops are unrolled in the trace  Now speed it up (trace compaction) Focus on limiting instruction count Branches are seen as jumps into or out of the trace  Problem: Significant overhead for parts that are not in the trace Unclear if it is feasible in practice

7 7/12 Superblocks  Similar to Trace Scheduling but: Single entrance, multiple exits  Tail duplication: Handle cases that exited the superblock Residual loop handling Could in itself be a superblock  Problem: Code size Worth the hassle?

8 8/12

9 9/12 Conditional instructions  Instruction that is executed depending on one of its arguments: BNEZ R1, L ADDU R2, R3, R0 L:  VS CMOVZ R2, R3, R1  Instruction is executed but results are not always written.  Should only be used for very small sequences, else use normal branch

10 10/12 Speculation  Compiler moves instructions before branch if: Data flow is not affected (optionally with use of renaming) Preserve exception behavior Avoid load/store address conflicts (no renaming for memory loc.)  Preserving exception behavior Mechanism to indicate an instruction is speculative Poison bit: raise exception when value is used Using Conditional instructions:  Requires In-Order instruction commit  Register renaming  Writeback at commit  Forwarding  Raise exceptions at commit

11 11/12 Speculation  if (A==0) A=B; else A=A+4; LDR1, 0(R3); load A BNEZ R1, L1; test A LDR1, 0(R2); then JL2; skip else L1:DADDIR1, R1, #4; else L2:SDR1, 0(R3); store A LDR1, 0(R3); load A LDR14, 0(R2); load B (speculative) BEQZR1, L3; branch if DADDIR14, R1, #4; else L3:SDR14, 0(R3); store A

12 12/12

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